參數(shù)資料
型號(hào): SC16C754BIA68
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.) with 64-byte FIFOs
封裝: SC16C754BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html<1<Always Pb-free,;SC16C754BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html&
文件頁(yè)數(shù): 16/51頁(yè)
文件大?。?/td> 253K
代理商: SC16C754BIA68
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
16 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.5.1
Interrupt mode operation
In interrupt mode (if any bit of IER[3:0] is ‘1’) the processor is informed of the status of the
receiver and transmitter by an interrupt signal, INT. Therefore, it is not necessary to
continuously poll the Line Status Register (LSR) to see if any interrupt needs to be
serviced.
Figure 9
shows interrupt mode operation.
6.5.2
Polled mode operation
In polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be
checked by polling the Line Status Register (LSR). This mode is an alternative to the FIFO
interrupt mode of operation where the status of the receiver and transmitter is
automatically known by means of interrupts sent to the CPU.
Figure 10
shows FIFO polled
mode operation.
Fig 9.
Interrupt mode operation
1
1
1
1
IIR
IER
THR
RHR
PROCESSOR
IOW / IOR
INT
002aaa230
Fig 10. FIFO polled mode operation
0
0
0
0
LSR
IER
THR
RHR
PROCESSOR
IOW / IOR
002aaa231
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