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| 型號： | SC16C754BIA68 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 收發(fā)器 |
| 英文描述： | 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.) with 64-byte FIFOs |
| 封裝： | SC16C754BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html<1<Always Pb-free,;SC16C754BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html& |
| 文件頁數(shù)： | 7/51頁 |
| 文件大小： | 253K |
| 代理商： | SC16C754BIA68 |
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SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
7 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
CSA
CSB
CSC
CSD
CTSA
CTSB
CTSC
CTSD
7
11
38
42
2
16
33
47
9
13
49
53
4
18
44
58
16
20
50
54
11
25
45
59
I
Chip Select (active LOW).
These pins enable data transfers between
the user CPU and the SC16C754B for the channel(s) addressed.
Individual UART sections (A, B, C, D) are addressed by providing a logic
LOW on the respective CSA through CSD pins.
I
Clear to Send (active LOW).
These inputs are associated with individual
UART channels A through D. A logic 0 (LOW) on the CTS pins indicates
the modem or data set is ready to accept transmit data from the
SC16C754B. Status can be tested by reading MSR[4]. These pins only
affect the transmit and receive operations when auto-CTS function is
enabled via the Enhanced Feature Register EFR[7] for hardware flow
control operation.
Data bus (bidirectional).
These pins are the 8-bit, 3-state data bus for
transferring information to or from the controlling CPU. D0 is the least
significant bit and the first data bit in a transmit or receive serial data
stream.
Data Set Ready (active LOW).
These inputs are associated with
individual UART channels A through D. A logic 0 (LOW) on these pins
indicates the modem or data set is powered-on and is ready for data
exchange with the UART. The state of these inputs is reflected in the
Modem Status Register (MSR).
D0 to D7
53, 54,
55, 56,
57, 58,
59, 60
1
17
32
48
3
15
34
46
68, 69,
70, 71,
72, 73,
74, 75
3
19
43
59
5
17
45
57
66, 67,
68, 1, 2,
3, 4, 5
I/O
DSRA
DSRB
DSRC
DSRD
DTRA
DTRB
DTRC
DTRD
10
26
44
60
12
24
46
58
I
O
Data Terminal Ready (active LOW).
These outputs are associated with
individual UART channels A through D. A logic 0 (LOW) on these pins
indicates that the SC16C754B is powered-on and ready. These pins can
be controlled via the Modem Control Register (MCR). Writing a logic 1 to
MCR[0] will set the DTR output to logic 0 (LOW), enabling the modem.
The output of these pins will be a logic 1 after writing a logic 0 to MCR[0],
or after a reset.
Signal and power ground.
GND
14, 28,
45, 61
6
12
37
43
16, 36,
56, 76
8
14
48
54
6, 23,
40, 57
15
21
49
55
I
INTA
INTB
INTC
INTD
O
Interrupt A, B, C, and D (active HIGH).
These pins provide individual
channel interrupts INTA through INTD. INTA through INTD are enabled
when MCR[3] is set to a logic 1, interrupt sources are enabled in the
Interrupt Enable Register (IER). Interrupt conditions include: receiver
errors, available receiver buffer data, available transmit buffer space, or
when a modem status flag is detected. INTA to INTD are in the
high-impedance state after reset.
Interrupt Select (active HIGH with internal pull-down).
INTSEL can be
used in conjunction with MCR[3] to enable or disable the 3-state
interrupts INTA to INTD or override MCR[3] and force continuous
interrupts. Interrupt outputs are enabled continuously by making this pin a
logic 1. Driving this pin LOW allows MCR[3] to control the 3-state
interrupt output. In this mode, MCR[3] is set to a logic 1 to enable the
3-state outputs. This pin is associated with LQFP80 and PLCC68
packages only. This pin is connected to GND internally on the LQFP64
package.
Input/Output Read strobe (active LOW).
A HIGH-to-LOW transition on
IOR will load the contents of an internal register defined by address bits
A[2:0] onto the SC16C754B data bus (D[7:0]) for access by external
CPU.
INTSEL
-
67
65
I
IOR
40
51
52
I
Table 2.
Symbol
Pin description
…continued
Pin
LQFP64 LQFP80 PLCC68
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SC16C754BIB80 | 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.) with 64-byte FIFOs |
| SC16C754BIBM | 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.) with 64-byte FIFOs |
| SC16C850IBS | 2.5 V to 3.3 V UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface |
| SC16C850IET | 2.5 V to 3.3 V UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface |
| SC16C850LIB | 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C754BIA68,512 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C754BIA68,518 | 功能描述:UART 接口集成電路 4CH. UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C754BIA68,529 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C754BIA68512 | 制造商:NXP Semiconductors 功能描述:IC QUAD UART FIFO 5MBPS 5.5V LCC-68 |
| SC16C754BIA68-S | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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