參數(shù)資料
型號: SC16C850IBS/Q900,5
廠商: NXP Semiconductors
文件頁數(shù): 14/55頁
文件大小: 0K
描述: IC UART SGL UNIV ASYNC 36-VFQFN
標(biāo)準(zhǔn)包裝: 1
特點: 可編程
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.5 V ~ 3.3 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 568-6566-6
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SC1
6
C850
Al
li
n
for
m
at
ion
pr
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ded
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this
do
cum
ent
i
s
sub
jec
tto
leg
a
ld
is
c
la
im
er
s.
NXP
B.V
.
2010.
Al
lr
ig
h
ts
re
s
e
rv
ed.
Produ
ct
d
a
ta
sheet
R
e
v
.2
1
N
o
vem
ber
2010
21
o
f55
N
X
P
Semi
conductor
s
SC16C850
2
.5
to
3.3
V
UART
with
1
28-
byt
e
FIFOs
and
IrDA
e
n
cod
e
r/dec
ode
r
Table 8.
SC16C850 internal registers
A2 A1 A0 Register
Default[1]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
General register set[2]
0
RHR
0xXX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
0
THR
0xXX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W
0
1
IER
0x00
CTS
interrupt[3]
RTS
interrupt[3]
Xoff
interrupt[3]
Sleep
modem
status
interrupt
receive line
status
interrupt
transmit
holding
register
interrupt
receive
holding
register
interrupt
R/W
0
1
0
FCR
0x00
RCVR
trigger
(MSB)
RCVR
trigger (LSB)
TX trigger
(MSB)[3]
TX trigger
reserved
XMIT FIFO
reset
RCVR FIFO
reset
FIFOs
enable
W
0
1
0
ISR
0x01
FIFOs
enabled
FIFOs
enabled
INT priority
bit 4
INT priority
bit 3
INT priority
bit 2
INT priority
bit 1
INT priority
bit 0
INT status
R
0
1
LCR
0x00
divisor latch
enable
set break
set parity
even parity
parity
enable
stop bits
word length
bit 1
word length
bit 0
R/W
1
0
MCR
0x00
clock
select[3]
IrDA enable
INT type
loopback
OP2
OP1
RTS
DTR
R/W
1
0
1
LSR
0x60
FIFO data
error
THR and
TSR empty
THR empty
break
interrupt
framing
error
parity error
overrun
error
receive data
ready
R
1
0
1
EFCR
0x00
reserved
Enable extra
feature bit 1
Enable extra
feature bit 0
Enable
TXLVLCNT/
RXLVLCNT
W
1
0
MSR
0xX0
CD
RI
DSR
CTS
ΔCD
ΔRI
ΔDSR
ΔCTS
R
1
SPR
0xFF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
Special register set[4]
0
DLL
0xXX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0
1
DLM
0xXX
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
Second special register set[6]
0
1
TXLVLCNT
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
1
0
RXLVLCNT
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
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