參數(shù)資料
型號: SC16C850IBS/Q900,5
廠商: NXP Semiconductors
文件頁數(shù): 28/55頁
文件大?。?/td> 0K
描述: IC UART SGL UNIV ASYNC 36-VFQFN
標(biāo)準(zhǔn)包裝: 1
特點(diǎn): 可編程
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.5 V ~ 3.3 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 568-6566-6
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
34 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
[1]
For 32-byte FIFO mode, refer to Section 7.3.
7.17 Flow Control Trigger Level High (FLWCNTH)
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control. Table 27 shows the FLWCNTH
register bit settings; see Section 6.5.
[1]
For 32-byte FIFO mode, refer to Section 7.3.
7.18 Flow Control Trigger Level Low (FLWCNTL)
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control. Table 28 shows the FLWCNTL
register bit settings; see Section 6.5.
[1]
For 32-byte FIFO mode, refer to Section 7.3.
7.19 Clock Prescaler (CLKPRES)
This register hold values for the clock prescaler.
Table 27.
FLWCNTH register bits description
Bit
Symbol
Description
7:0
FLWCNTH[7:0]
This register stores the programmable HIGH threshold level for
hardware and software flow control for 128-byte FIFO mode[1].
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Table 28.
FLWCNTL register bits description
Bit
Symbol
Description
7:0
FLWCNTL[7:0]
This register stores the programmable LOW threshold level for
hardware and software flow control for 128-byte FIFO mode[1].
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Table 29.
Clock Prescaler register bits description
Bit
Symbol
Description
7:4
CLKPRES[7:4]
reserved
3:0
CLKPRES[3:0]
Clock Prescaler value. Reset to 0.
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