參數(shù)資料
型號: SC16C850IBS/Q900,5
廠商: NXP Semiconductors
文件頁數(shù): 33/55頁
文件大小: 0K
描述: IC UART SGL UNIV ASYNC 36-VFQFN
標(biāo)準(zhǔn)包裝: 1
特點(diǎn): 可編程
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.5 V ~ 3.3 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 568-6566-6
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
39 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
10. Dynamic characteristics
[1]
Applies to external clock, crystal oscillator max 24 MHz.
[2]
Maximum frequency =
[3]
10 % of the data bus output voltage level.
[4]
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
Table 37.
Dynamic characteristics - Intel or 16 mode
Tamb = 40 °C to +85 °C; tolerance of VDD ± 10 %; unless otherwise specified.
Symbol
Parameter
Conditions
VDD =2.5 V
VDD =3.3 V
Unit
Min
Max
Min
Max
tWH
pulse width HIGH
6
-
6
-
ns
tWL
pulse width LOW
6
-
6
-
ns
tw(clk)
clock pulse width
12.5
-
12.5
-
ns
fXTAL1
frequency on pin XTAL1
-80
-
80
MHz
tsu(A)
address set-up time
10
-
5
-
ns
th(A)
address hold time
10
-
5
-
ns
td(CS-IOR)
delay time from CS to IOR
10
-
5
-
ns
tw(IOR)
IOR pulse width time
35
-
26
-
ns
th(IOR-CS)
hold time from IOR to chip select
0
-
0
-
ns
td(IOR)
IOR delay time
10
-
10
-
ns
td(IOR-Q)
delay time from IOR to data output
25 pF load
-
35
-
26
ns
tdis(IOR-QZ)
disable time from IOR to
high-impedance data output[3]
25 pF load
-
17
-
15
ns
td(CSL-IOWL)
delay time from CS LOW to
IOW LOW
10
-
5
-
ns
tw(IOW)
IOW pulse width time
15
-
20
-
ns
th(IOW-CS)
hold time from IOW to CS
0-
ns
td(IOW)
IOW delay time
15
-
20
-
ns
tsu(D-IOWH)
set-up time from data input to
IOW HIGH
10
-
5
-
ns
th(IOWH-D)
data input hold time after IOW HIGH
10
-
5
-
ns
td(IOW-Q)
delay time from IOW to data output
25 pF load
-
40
-
33
ns
td(modem-INT) delay time from modem to INT
25 pF load
-
35
-
24
ns
td(IOR-INTL)
delay time from IOR to INT LOW
25 pF load
-
35
-
24
ns
td(stop-INT)
delay time from stop to INT
25 pF load
-1TRCLK
s
td(start-INT)
delay time from start to INT
25 pF load
-1TRCLK
s
td(IOW-TX)
delay time from IOW to TX
25 pF load
8TRCLK
24TRCLK
8TRCLK
24TRCLK s
td(IOW-INTL)
delay time from IOW to INT LOW
25 pF load
-
55
-
45
ns
tw(RESET)
pulse width on pin RESET
10
-
10
-
ns
N
baud rate divisor
1
(216
1)
1
(216
1)
1
t
wclk
()
---------------
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