參數(shù)資料
型號(hào)： SC16C850VIBS
廠商： NXP Semiconductors N.V.
元件分類： 收發(fā)器
英文描述： 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface
封裝： SC16C850VIBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;SC16C850VIBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁(yè)數(shù)： 26/48頁(yè)
文件大?。?/td> 338K
代理商： SC16C850VIBS
SC16C850V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 19 January 2011
26 of 48
NXP Semiconductors
SC16C850V
Single UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Table 19.
MCR[5]
0
1
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C850V and the CPU.
Table 20.
Bit
7
Interrupt output control
INT output
active
open-source
Line Status Register bits description
Symbol
Description
LSR[7]
FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error or break indication is in the
current FIFO data. This bit is cleared when there are no remaining error flags
associated with the remaining data in the FIFO.
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a
logic 1 whenever the transmit holding register and the transmit shift register are
both empty. It is reset to logic 0 whenever either the THR or TSR contains a data
character. In the FIFO mode, this bit is set to logic 1 whenever the transmit FIFO
and transmit shift register are both empty.
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator. This bit
indicates that the UART is ready to accept a new character for transmission. In
addition, this bit causes the UART to issue an interrupt to CPU when the THR
interrupt enable is set. The THR bit is set to a logic 1 when a character is
transferred from the transmit holding register into the transmitter shift register.
The bit is reset to a logic 0 concurrently with the loading of the transmitter holding
register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is
empty; it is cleared when at least 1 byte is written to the transmit FIFO.
LSR[4]
Break interrupt.
logic 0 = no break condition (normal default condition)
logic 1 = the receiver received a break signal (RX was a logic 0 for one
character frame time). In the FIFO mode, only one break character is loaded
into the FIFO.
LSR[3]
Framing error.
logic 0 = no framing error (normal default condition)
logic 1 = framing error. The receive character did not have a valid stop bit(s). In
the FIFO mode, this error is associated with the character at the top of the
FIFO.
LSR[2]
Parity error.
logic 0 = no parity error (normal default condition
logic 1 = parity error. The receive character does not have correct parity
information and is suspect. In the FIFO mode, this error is associated with the
character at the top of the FIFO.
LSR[1]
Overrun error.
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error. A data overrun error occurred in the Receive Shift
Register. This happens when additional data arrives while the FIFO is full. In
this case, the previous data in the shift register is overwritten. Note that under
this condition, the data byte in the Receive Shift Register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
6
5
4
3
2
1
相關(guān)PDF資料
PDF描述
SC16C852LIB 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
SC16C852LIBS 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
SC16C852LIET 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
SC16C852SVIET 1.8 V dual UART, 20 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface
SC16C852VIET 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and XScale VLIO bus interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SC16C850VIBS,115 功能描述:UART 接口集成電路 1.8V 1 CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C850VIBS,128 功能描述:UART 接口集成電路 1.8V 1 CH UART 128B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C850VIBS,151 功能描述:UART 接口集成電路 1.8V 1 CH UART 128B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C850VIBS,157 功能描述:UART 接口集成電路 1.8V 1 CH UART 128B RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C850VIBS-F 功能描述:UART 接口集成電路 1.8V 1 CH UART 128B FIFO VLIO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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