參數(shù)資料
型號： SC16C852VIET,151
廠商： NXP Semiconductors
文件頁數(shù)： 13/55頁
文件大小： 0K
描述： IC UART DUAL W/FIFO 36TFBGA
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： 可編程
通道數(shù)： 2，DUART
FIFO's： 128 字節(jié)
規(guī)程： RS485
電源電壓： 2.5V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 36-TFBGA
供應(yīng)商設(shè)備封裝： 36-TFBGA（3.5x3.5）
包裝： 托盤
其它名稱： 568-5662
935282518151
SC16C852VIET,151-ND
SC16C852VIET-S
SC16C852VIET-S-ND
SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
20 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
6.14.3.2
Auto address detection
If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register contains the
address byte), the receiver will try to detect an address byte that matches the
programmed character in the XOFF2 register. If the received byte is a data byte or an
address byte that does not match the programmed character in the XOFF2 register, the
receiver will discard these data. Upon receiving an address byte that matches the Xoff2
character, the receiver will be automatically enabled if not already enabled, and the
address character is pushed into the RX FIFO along with the parity bit (in place of the
parity error bit). The receiver also generates a line status interrupt (IER[2] must be set to
logic 1 at this time). The receiver will then receive the subsequent data from the ‘master’
station until being disabled by the controller after having received a message from the
‘master’ station.
If another address byte is received and this address byte does not match Xoff2 character,
the receiver will be automatically disabled and the address byte is ignored. If the address
byte matches Xoff2 character, the receiver will put this byte in the RX FIFO along with the
parity bit in the parity error bit (LSR bit 2).
7.
Register descriptions
Table 9 details the assigned bit functions for the SC16C852V internal registers. The
assigned bit functions are more fully defined in Section 7.1 through Section 7.23.
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