參數(shù)資料
型號(hào)： SC16C852VIET,151
廠商： NXP Semiconductors
文件頁數(shù)： 19/55頁
文件大?。?/td> 0K
描述： IC UART DUAL W/FIFO 36TFBGA
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： 可編程
通道數(shù)： 2，DUART
FIFO's： 128 字節(jié)
規(guī)程： RS485
電源電壓： 2.5V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 36-TFBGA
供應(yīng)商設(shè)備封裝： 36-TFBGA（3.5x3.5）
包裝： 托盤
其它名稱： 568-5662
935282518151
SC16C852VIET,151-ND
SC16C852VIET-S
SC16C852VIET-S-ND
SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
26 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
[1]
For 128-byte FIFO mode, refer to Section 7.16, Section 7.17, Section 7.18.
[2]
For 128-byte FIFO mode, refer to Section 7.15, Section 7.17, Section 7.18.
[1]
When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL; see Section 6.4 “FIFO operation”.
[1]
When RXINTLVL or TXINTLVL or FLWCNTH or FLWCNTL contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL; see Section 6.4 “FIFO operation”.
3
(cont.)
Transmit operation in mode ‘1’: When the SC16C852V is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY signal will be a logic 1 when
the transmit FIFO is completely full, see Section 6.10 “DMA operation”. It will
be a logic 0 when the trigger level has been reached.
Receive operation in mode ‘1’: When the SC16C852V is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,
or a Receive Time-Out has occurred, the RXRDY signal will go to a logic 0.
Once activated, it will go to a logic 1 after there are no more characters in the
FIFO.
2
FCR[2]
XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
1
FCR[1]
RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
Table 12.
RCVR trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level in 32-byte FIFO mode[1]
0
8 bytes
0
1
16 bytes
1
0
24 bytes
1
28 bytes
Table 13.
TX FIFO trigger levels
FCR[5]
FCR[4]
TX FIFO trigger level in 32-byte FIFO mode[1]
0
16 bytes
0
1
8 bytes
1
0
24 bytes
1
30 bytes
Table 11.
FIFO Control Register bits description …continued
Bit
Symbol
Description
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