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參數(shù)資料
| 型號： | SC16IS741IPW,118 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART SGL I2C BUS SPI 16TSSOP |
| 標準包裝： | 2,500 |
| 系列： | * |
SC16IS741_1
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 29 April 2010
4 of 52
NXP Semiconductors
SC16IS741
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
6.
Pinning information
6.1 Pinning
6.2 Pin description
a. I2C-bus interface
b. SPI interface
Fig 3.
Pin configuration for TSSOP16
SC16IS741IPW
VDD
XTAL2
A0
XTAL1
A1
RESET
n.c.
RX
SCL
TX
SDA
CTS
IRQ
RTS
I2C
VSS
002aaf158
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
SC16IS741IPW
VDD
XTAL2
CS
XTAL1
SI
RESET
SO
RX
SCLK
TX
VSS
CTS
IRQ
RTS
SPI
VSS
002aaf159
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2.
Pin description
Symbol
Pin
Type Description
VDD
1
-
power supply
CS/A0
2
I
SPI chip select or I2C-bus device address select A0. If SPI
configuration is selected by I2C/SPI pin, this pin is the SPI chip select
pin (Schmitt-trigger, active LOW). If I2C-bus configuration is selected
by I2C/SPI pin, this pin along with A1 pin allows user to change the
device’s base address.
SI/A1
3
I
SPI data input pin or I2C-bus device address select A1. If SPI
configuration is selected by I2C/SPI pin, this is the SPI data input pin.
If I2C-bus configuration is selected by I2C/SPI pin, this pin along with
A0 pin allows user to change the device’s base address. To select the
device address, please refer to Table 28.
SO
4
O
SPI data output pin. If SPI configuration is selected by I2C/SPI pin,
this is a 3-stateable output pin. If I2C-bus configuration is selected by
I2C/SPI pin, this pin function is undefined and must be left as n.c. (not
connected).
SCL/SCLK
5
I
I2C-bus or SPI input clock.
SDA
6
I/O
I2C-bus data input/output, open-drain if I2C-bus configuration is
selected by I2C/SPI pin. If SPI configuration is selected then this pin
is an undefined pin and must be connected to VSS.
IRQ
7
O
Interrupt (open-drain, active LOW). Interrupt is enabled when
interrupt sources are enabled in the Interrupt Enable Register (IER).
Interrupt conditions include: change of state of the input pins, receiver
errors, available receiver buffer data, available transmit buffer space,
or when a modem status flag is detected. An external resistor (1 k
Ω
for 3.3V, 1.5k
Ω for 2.5 V) must be connected between this pin and
VDD.
I2C/SPI
8I
I2C-bus or SPI interface select. I2C-bus interface is selected if this pin
is at logic HIGH. SPI interface is selected if this pin is at logic LOW.
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