Revision 3.0
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G
Video Processor Module
(Continued)
Table 6-4. F4BAR0: Video Processor Configuration Registers Summary
F4BAR0+
Memory
Offset
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 6-7)
00h-03h
04h-07h
08h-0Bh
0Ch-0Fh
10h-13h
14h-17h
18h-1Bh
1Ch-1Fh
20h-23h
24h-27h
28h-2Bh
2Ch-2Fh
30h-33h
34h-37h
38h-3Bh
3Ch-3Fh
40h-43h
44h-47h
48h-4Bh
4Ch-4Fh
50h-53h
54h-57h
58h-5Bh
5Ch-5Fh
60h-63h
64h-67h
68h-6Bh
6Ch-6Fh
70h-73h
74h-77h
78h-7Bh
7Ch-7Fh
80h-83h
84h-87h
88h-8Bh
8Ch-8Fh
90h-93h
94h-97h
98h-3FFh
400h-403h
404h-407h
408h-40Bh
40Ch-41Fh
420h-423h
424h-427h
428h-43Bh
43Ch-43Fh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W
---
RO
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
---
R/W
---
R/W
---
R/W
R/W
---
R/W
Video Configuration Register
Display Configuration Register
Video X Position Register
Video Y Position Register
Video Upscaler Register
Video Color Key Register
Video Color Mask Register
Palette Address Register
Palette Data Register
Reserved
Miscellaneous Register
PLL2 Clock Select Register
Reserved
Reserved
Reserved
Video Downscaler Control Register
Video Downscaler Coefficient Register
CRC Signature Register
Device and Revision Identification
Video De-Interlacing and Alpha Control Register
Cursor Color Key Register
Cursor Color Mask Register
Cursor Color Register 1
Cursor Color Register 2
Alpha Window 1 X Position Register
Alpha Window 1 Y Position Register
Alpha Window 1 Color Register
Alpha Window 1 Control Register
Alpha Window 2 X Position Register
Alpha Window 2 Y Position Register
Alpha Window 2 Color Register
Alpha Window 2 Control Register
Alpha Window 3 X Position Register
Alpha Window 3 Y Position Register
Alpha Window 3 Color Register
Alpha Window 3 Control Register
Video Request Register
Alpha Watch Register
Reserved
Video Processor Display Mode Register
Reserved
Video Processor Test Mode Register
Reserved
GenLock Register
GenLock Delay Register
Reserved
Continuous GenLock Time-out Register
00000000h
x0000000h
00000000h
00000000h
00000000h
00000000h
00000000h
xxxxxxxxh
xxxxxxxxh
---
00001400h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
xxxxx100h
0000015xh
00060000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
001B0017h
00000000h
---
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
---
1FFF1FFFh
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32
32
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32