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344
Revision 3.0
G
Video Processor Module
(Continued)
14:8
m (Defines m PLL2 Value).
Relevant when SEL_REG_CAL (bit 20) = 1. The following formula is used for calculating the
frequency using m and n values:
Fvco
= OSCCLK * Km/Kn
Km
= m + 1
Kn
= n + 1
OSCCLK = 27 MHz
Reserved
n (Defines n PLL2 Value).
Relevant when SEL_REG_CAL (bit 20) = 1. The following formula is used for calculating the fre-
quency using m and n values:
Fvco
= OSCCLK * Km/Kn
Km
= m + 1
Kn
= n + 1
OSCCL
= 27 MHz
7:4
3:0
Offset 30h-33h
Reserved
Reset Value: 00000000h
Offset 34h-37h
Reserved
Reset Value: 00000000h
Offset 38h-3Bh
Reserved
Reset Value: 00000000h
Offset 3Ch-3Fh
Controls the characteristics of the integrated video downscaler.
Video Downscaler Control Register (R/W)
Reset Value: 00000000h
31:7
6
Reserved
DTS (Downscale Type Select).
0: Type A (Downscale formula is 1/m+1, m pixels are dropped, 1 pixel is kept).
1: Type B (Downscale formula is m/m+1, m pixels are kept, 1 pixel is dropped).
Reserved
DFS (Downscale Factor Select).
Determines the downscale factor to be programmed into these bits, where m is used to
derive the desired downscale factor depending on bit 6 (DTS).
DCF (Downscaler and Filtering).
Enables/disables downscaler and filtering logic.
0: Disable.
1: Enable.
Note:
No downscaling support for RGB 5:6:5 and YUV 4:2:0 video formats.
5
4:1
0
Offset 40h-43h
Indicates filter coefficients. The filters can be programmed independently to increase video quality when the downscaler is implemented.
Valid values for each filter coefficient are 0-15. The sum of coefficients must be 16. FLT_CO_4 is used with the earliest pixels and
FLT_CO_1 is used with the latest. Only luminance values of pixels are filtered.
Video Downscaler Coefficient Register (R/W)
Reset Value: 00000000h
31:28
27:24
23:20
19:16
15:12
11:8
7:4
3:0
Reserved
FLT_CO_4 (Filter Coefficient 4).
For the tap-4 filter.
Reserved
FLT_CO_3 (Filter Coefficient 3).
For the tap-3 filter.
Reserved
FLT_CO_2 (Filter Coefficient 2).
For the tap-2 filter.
Reserved
FLT_CO_1 (Filter Coefficient 1).
For the tap-1 filter.
Offset 44h-47h
Signature values stored in this register can be read by the host. This register is used for test purposes.
CRC Signature Register (R/W)
Reset Value: xxxxx100h
31:8
SIG_VALUE (Signature Value). (Read Only)
A 24-bit signature value is stored in this bit field and can be read at any time.
The signature is produced from the RGB data output of the mixer. This bit field is used for test purpose only.
See SIGN_EN (bit 0) description for more information.
Reserved
7:3
Table 6-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description