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80
Revision 3.0
G
3.0
The General Configuration block includes registers for:
General Configuration Block
Pin Multiplexing and Miscellaneous Configuration
WATCHDOG Timer
High-Resolution Timer
Clock Generators
A selectable interrupt is shared by all these functions.
3.1
Registers of the General Configuration block are I/O
mapped in a 64-byte address range. These registers are
physically connected to the internal Fast-PCI bus, but do
CONFIGURATION BLOCK ADDRESSES
not have a register block in PCI configuration space (i.e.,
they do not appear to software as PCI registers).
After system reset, the Base Address register is located at
I/O address 02EAh. This address can be used only once.
Before accessing any PCI registers, the BOOT code must
program this 16-bit register to the I/O base address for the
General Configuration block registers. All subsequent
writes to this address, are ignored until system reset.
Note:
Location of the General Configuration Block can-
not be determined by software. See the
SC2200
Thin Client On a Chip device errata
document.
Reserved bits in the General Configuration block should
read as written unless otherwise specified..
Table 3-1. General Configuration Block Register Summary
Offset
Width
(Bits)
Type
Name
Reset Value
Reference
00h-01h
16
R/W
WDTO.
WATCHDOG Timeout
0000h
Page 89
02h-03h
16
R/W
WDCNFG.
WATCHDOG Configuration
0000h
Page 89
04h
8
R/WC
WDSTS.
WATCHDOG Status
00h
Page 90
05h-07h
---
---
RSVD.
Reserved
---
---
08h-0Bh
32
RO
TMVALUE.
TIMER Value
xxxxxxxxh
Page 92
0Ch
8
R/W
TMSTS.
TIMER Status
00h
Page 92
0Dh
8
R/W
TMCNFG.
TIMER Configuration
00h
Page 92
0Eh-0Fh
---
---
RSVD.
Reserved
---
---
10h
8
RO
MCCM.
Maximum Core Clock Multiplier
Strapped Value
Page 96
11h
---
---
RSVD.
Reserved
---
---
12h
8
R/W
PPCR.
PLL Power Control
2Fh
Page 96
13h-17h
---
---
RSVD.
Reserved
---
---
18h-1Bh
32
R/W
PLL3C.
PLL3 Configuration
E1040005h
Page 97
1Ch-1Dh
---
---
RSVD.
Reserved
---
---
1Eh-1Fh
16
R/W
CCFC.
Core Clock Frequency Control
Strapped Value
Page 97
20h-2Fh
---
---
RSVD.
Reserved
---
---
30h-33h
32
R/W
PMR.
Pin Multiplexing Register
00000000h
Page 81
34h-37h
32
R/W
MCR.
Miscellaneous Configuration Register
00000001h
Page 85
38h
8
R/W
INTSEL.
Interrupt Selection
00h
Page 87
39h-3Bh
---
---
RSVD.
Reserved
---
---
3Ch
8
RO
IID.
IA On a Chip ID
xxh
Page 87
3Dh
8
RO
REV.
Revision
xxh
Page 87
3Eh-3Fh
16
RO
CBA.
Configuration Base Address
xxxxh
Page 87