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46
Revision 3.0
G
Signal Definitions
(Continued)
AK5
GPWIO1
I/O
(PU
100
)
IN
Ts
,
TS
2/14
V
SB
---
AK6
6, 2
PWRCNT1
O
OD
14
V
SB
---
AK7
V
SS
GND
---
---
---
AK8
IRRX1
I
IN
TS
V
SB
PMR[6] = 0
SIN3
I
IN
TS
V
IO
PMR[6] =1
AK9
6
MD1
I/O
IN
T
,
TS
2/5
V
IO
---
AK10
V
SS
GND
---
---
---
AK11
6
MD7
I/O
IN
T
,
TS
2/5
V
IO
---
AK12
RASA#
O
O
2/5
V
IO
---
AK13
V
IO
PWR
---
---
---
AK14
BA1
O
O
2/5
V
IO
---
AK15
MA2
O
O
2/5
V
IO
---
AK16
V
IO
PWR
---
---
AK17
6
MD35
I/O
IN
T
,
TS
2/5
V
IO
---
AK18
6
MD46
I/O
IN
T
,
TS
2/5
V
IO
---
AK19
V
IO
PWR
---
---
---
AK20
6
MD43
I/O
IN
T
,
TS
2/5
V
IO
---
AK21
DQM5
O
O
2/5
V
IO
---
AK22
V
SS
GND
---
---
---
AK23
MA5
O
O
2/5
V
IO
---
AK24
6
MD15
I/O
IN
T
,
TS
2/5
V
IO
---
AK25
V
SS
GND
---
---
---
AK26
6
MD14
I/O
IN
T
,
TS
2/5
V
IO
---
AK27
6
MD12
I/O
IN
T
,
TS
2/5
V
IO
---
AK28
SDCLK_OUT
O
O
2/5
V
IO
---
AK29
6
MD16
I/O
IN
T
,
TS
2/5
V
IO
---
AK30
V
SS
GND
---
---
---
AK31
V
IO
PWR
---
---
---
AL1
V
SS
GND
---
---
---
AL2
V
IO
PWR
---
---
---
AL3
V
BAT
PWR
---
---
---
AL4
LED#
O
OD
14
V
SB
---
AL5
V
SB
PWR
---
---
---
AL6
V
SBL
PWR
---
---
---
AL7
6, 2
PWRCNT2
O
OD
14
V
SB
---
AL8
SDATA_IN2
I
IN
TS
V
SB
F3BAR0+Memory
Offset 08h[21] = 1
AL9
6
MD2
I/O
IN
T
,
TS
2/5
V
IO
---
AL10
6
MD4
I/O
IN
T
,
TS
2/5
V
IO
---
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration
AL11
DQM0
O
O
2/5
V
IO
---
AL12
CS0#
O
O
2/5
V
IO
---
AL13
V
SS
GND
---
---
---
AL14
MA0
O
O
2/5
V
IO
---
AL15
DQM4
O
O
2/5
V
IO
---
AL16
V
SS
GND
---
---
---
AL17
6
MD38
I/O
IN
T
,
TS
2/5
V
IO
---
AL18
6
MD39
I/O
IN
T
,
TS
2/5
V
IO
---
AL19
V
SS
GND
---
---
---
AL20
6
MD44
I/O
IN
T
,
TS
2/5
V
IO
---
AL21
6
MD40
I/O
IN
T
,
TS
2/5
V
IO
---
AL22
CKEA
O
O
2/5
V
IO
---
AL23
MA7
O
O
2/5
V
IO
---
AL24
MA4
O
O
2/5
V
IO
---
AL25
6
MD8
I/O
IN
T
,
TS
2/5
V
IO
---
AL26
6
MD10
I/O
IN
T
,
TS
2/5
V
IO
---
AL27
6
MD9
I/O
IN
T
,
TS
2/5
V
IO
---
AL28
MA12
O
O
2/5
V
IO
---
AL29
6
MD23
I/O
IN
T
,
TS
2/5
V
IO
---
AL30
V
IO
PWR
---
---
---
AL31
V
SS
GND
---
---
---
1.
For Buffer Type definitions, refer to Table 8-9 "Buffer Types" on page
364.
Is 5V tolerant (ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#,
PD[7:0], PE, SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#,
PWRCNT[2:1]).
The TFT_PRSNT strap determines the power-on reset (POR) state of
PMR[23].
The LPC_ROM strap determines the power-on reset (POR) state of
PMR[14] and PMR[22].
May need 5V tolerant protection at system level (DDC_SCL,
DDC_SDA).
Is back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1,
DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3,
ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], PE,
SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]).
2.
3.
4.
5.
6.
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration
Table 2-4.
481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)