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參數(shù)資料
| 型號(hào)： | SD014EVK |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 11/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION CLC014 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，線纜均衡器 |
| 已用 IC / 零件： | CLC014 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | CLC014AJE-TR13-ND - IC CABLE EQUALIZER ADAPT 14-SOIC CLC014AJE-ND - IC CABLE EQUALIZER ADAPTV 14SOIC |
OBSOLETE
SNLS010E – JUNE 1998 – REVISED APRIL 2013
Figure 31. Typical Measurement Setup
Evaluation Board
Evaluation boards are available for a nominal charge that demonstrate the basic operation of the SDI/SDV/SDH
devices. The evaluation boards can be ordered through Texas Instruments' Distributors. Supplies are limited,
please check for current availability.
The SD014EVK evaluation kit for the CLC014, Adaptive Cable Equalizer for High-Speed Data Recovery,
provides an operating environment in which the cable equalizer can be evaluated by system / hardware
designers. The evaluation board has all the needed circuitry and connectors for easy connection and checkout of
the device circuit options as discussed in the CLC014 datasheet. A schematic, parts list and pictorial drawing are
provided with the board.
Device Datasheet and / or EVK User Manual
View a picture of the EVK
View the EVK Schematic
View the top assembly drawing and BOM
View the bottom assembly drawing and BOM
PCB LAYOUT
The CLC014 requires proper high-speed layout techniques to obtain best results. A few recommended layout
rules to follow for best results when using the CLC014 Adaptive Cable Equalizer are:
1. Use a ground plane.
2. Decouple power pins with 0.01
μF capacitors placed ≤ 0.1” (3mm) from the power pins.
3. Design transmission lines to the inputs and outputs.
4. Route outputs away from inputs.
5. Remove ground plane
≥ 0.025” (0.06mm) from the input and output pads.
Copyright 1998–2013, Texas Instruments Incorporated
19
Product Folder Links: CLC014
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