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參數資料
| 型號： | SD014EVK |
| 廠商： | National Semiconductor |
| 文件頁數： | 16/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION CLC014 |
| 標準包裝： | 1 |
| 主要目的： | 接口，線纜均衡器 |
| 已用 IC / 零件： | CLC014 |
| 已供物品： | 板 |
| 相關產品： | CLC014AJE-TR13-ND - IC CABLE EQUALIZER ADAPT 14-SOIC CLC014AJE-ND - IC CABLE EQUALIZER ADAPTV 14SOIC |
OBSOLETE
SNLS010E – JUNE 1998 – REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS
(VCC = +5V, VEE = 0V, signal source swing = 0.8 Vpp
(1), C
AEC = 100 pF)
Min/Max
Typ
Min/Max
Parameter
Conditions
40°C to
Units
+25°C
+85°C
DYNAMIC PERFORMANCE
Residual Jitter
100 meters Belden 8281
270 Mbps PRN (2)
150
250
400
pspp
200 meters Belden 8281
270 Mbps PRN (2)
180
250
400
pspp
300 meters Belden 8281
270 Mbps PRN (3)(2)
350
500
750
pspp
Equalization Time Constant
100 meters Belden 8281
CAEC = 100 pF
(4)
1.5
_
μs
200 meters Belden 8281
CAEC = 100 pF
(4)
2.0
_
μs
300 meters Belden 8281
CAEC = 100 pF
(4)
3.2
_
μs
output rise and fall time (20%–80%)
Rcollector = 75
750
_
ps
output duty cycle distortion
30
_
ps
minimum average transition density
1/50
_
trans/ns
maximum average data rate
150m Belden 8281 (5)
650
_
Mbps
VCC Jitter Sensitivity
27 MHz
0.85
_
ns/V
270 MHz
1.90
_
ns/V
VEE Jitter Sensitivity
27 MHz
0.55
_
ns/V
270 MHz
1.45
_
ns/V
STATIC PERFORMANCE
Supply Current (Includes Output Current)
VAEC = 0V
(3)
58
48/68
40/75
mA
VAEC = 0.4V
(3)
53
43/64
37/70
mA
Input and Output Parameters
DO/DO output current
10
8.7/11.3
8.0/12
mA
DO/DO output voltage swing
Rcollector = 75
(3)
750
650/850
600/900
mV
DI/DI common mode voltage
3.4
_
V
AEC differential voltage
Belden 8281
1.5
_
mV/meter
AEC+/AEC
common mode
3.6
_
V
output eye monitor (OEM) bias potential
3.2
_
V
carrier detect (CD) current output-HIGH
CD VOH = 4.5V
400
_
μA
carrier detect (CD) current output-LOW
CD VOL = 0.5V
600
_
μA
MUTE voltage input-HIGH
(3)
1.8
2.0
V
MUTE voltage input-LOW
(3)
1.2
0.8
V
MUTE current input-HIGH
VIH = 5V
(3)
5.0
±100
±500
nA
MUTE current input-LOW
VIL = 0V
(3)
0.2
±100
±500
nA
(1)
These specifications assume an 800 mVpp signal at the cable input. Levels above and below 800 mV are allowable, but performance
may vary. The cable will attenuate the signal prior to entering the equalizer.
(2)
Peak-to-peak jitter is defined as 6 times the rms jitter.
(3)
J-level: spec. is 100% tested at +25°C.
(4)
For more information, see OPERATION and Design Guidelines.
(5)
50% eye opening.
4
Copyright 1998–2013, Texas Instruments Incorporated
Product Folder Links: CLC014
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