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參數(shù)資料
| 型號： | SD014EVK |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION CLC014 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，線纜均衡器 |
| 已用 IC / 零件： | CLC014 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | CLC014AJE-TR13-ND - IC CABLE EQUALIZER ADAPT 14-SOIC CLC014AJE-ND - IC CABLE EQUALIZER ADAPTV 14SOIC |
OBSOLETE
SNLS010E – JUNE 1998 – REVISED APRIL 2013
Output Interfacing
The outputs DO and DO produce ECL logic levels when the recommended output termination networks are
used. The DO and DO pins are not complementary emitter coupled logic outputs. Instead, the outputs are
taken off of the collectors of the transistors. Therefore, care must be taken to meet the interface threshold levels
required by ECL families. Recommended interfaces for standard ECL families are shown in the following circuits.
DIFFERENTIAL LOAD-TERMINATED OUTPUT INTERFACE
Figure 21 shows a recommended circuit for implementing a differential output that is terminated at the load. A
diode or 75
resistor provides a voltage drop from the positive supply (+5V for PECL or Ground for ECL
operation) to establish proper ECL levels. The resistors terminate the cable to the characteristic impedance. The
output voltage swing is determined by the CLC014 output current (10 mA) times the termination resistor. For the
circuit in Figure 21, the nominal output voltage swing is 750 mV.
Figure 21. Differential Load Terminated
Output Interface
DIFFERENTIAL SOURCE-TERMINATED OUTPUT INTERFACE
Figure 22 is similar to Figure 21 except that the termination is provided at the source. This configuration may also
be used for single-ended applications. However, the unused output must still be terminated as shown.
Figure 22. Differential Source Terminated
Output Interface
12
Copyright 1998–2013, Texas Instruments Incorporated
Product Folder Links: CLC014
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