參數(shù)資料
型號(hào)： SI3000SSI-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 20/34頁
文件大?。?/td> 0K
描述： BOARD EVAL PARALLEL PORT SI3000
標(biāo)準(zhǔn)包裝： 1
主要目的： 音頻編解碼器
已用 IC / 零件： SI3000
已供物品： 主板和子卡組套
Si3000
Rev. 1.4
27
4. Pin Descriptions: Si3000
Pin #
Pin Name
Description
1
SPKRR
Speaker Right Output.
Analog output capable of driving a 60
load.
2
MBIAS
Microphone bias output.
3
HDST
Handset Input/Output.
Handset analog input/output.
4
SDI
Serial Port Data In.
Serial communication and control data that is generated by the System DSP to the
Si3000.
5
SDO
Serial Port Data Out.
Serial communication data that is provided by the Si3000 to the system DSP.
6
FSYNC
Frame Sync Output.
Data framing signal that is used to indicate the start and stop of a communication data
frame.
7
MCLK
Master Clock Input.
High speed master clock input. Generally supplied by the system crystal clock or DSP.
8
SCLK
Serial Port Bit Clock Input/Output.
Controls the serial data on SDO and latches the data on SDI. This pin is an input in
slave mode and an output in master mode.
9
RESET
Reset.
An active low input that is used to reset all control registers to a defined initialized
state. Also used to bring the Si3000 out of sleep mode.
10
MIC
MIC Input.
Microphone level or line level input. This input contains selectable gain of 0, 10, 20, or
30 dB with a full scale input level of 1 VRMS.
11
LINEI
Line Input.
Line level input with selectable gain of 0, 10, or 20 dB. The full scale input level is
1 VRMS.
12
VD
Digital Supply Voltage.
Provides the digital supply voltage to the Si3000. Nominally either 5 or 3.3 V and
within 0.6 V of VA.
2
1
3
4
5
6
7
8
15
16
14
13
12
11
10
9
SPKRR
MBIA S
HDST
SDI
SDO
MCLK
SCLK
LINEO
GND
V
A
V
D
LINEI
MIC
RESET
SPKRL
FSY NC
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