
Si3000
8
Rev. 1.4
Figure 2. Serial Interface Timing Diagram
Table 7. Switching Characteristics—Serial Interface
(VA, VD = 5 V ±5% or 3.3 V ±10%, TA = 0 to 70°C, CL = 20 pF)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Cycle Time, SCLK
tc
354
1/256 Fs
—
ns
SCLK Duty Cycle
tdty
—
50
—
%
Delay Time, SCLK
to FSYNC
td1
—
10
ns
Delay Time, SCLK
to SDO Valid
td2
—
20
ns
Delay Time, SCLK
to FSYNC
td3
—
10
ns
Setup Time, SDI, before SCLK
tsu
25
—
ns
Hold Time, SDI, after SCLK
th
20
—
ns
Setup Time, FSYNC (mode 2) before
MCLK
tsu
25
—
ns
Hold Time, FSYNC (mode 2) after
MCLK
th
20
—
ns
Note:
All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V
SCLK
td1
VOH
VOL
FSYNC
(mode 0)
FSYNC
(mode 1)
td3
16 Bit
SDO
16 Bit
SDI
D0
D1
tsu
th
td2
FSYNC
(mode 2)
D0
... D2
High-Z
D15
D14
D1
D0
D15
D14
tc