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參數(shù)資料
型號: SI3000SSI-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 32/34頁
文件大小: 0K
描述: BOARD EVAL PARALLEL PORT SI3000
標(biāo)準(zhǔn)包裝: 1
主要目的: 音頻編解碼器
已用 IC / 零件: SI3000
已供物品: 主板和子卡組套
Si3000
Rev. 1.4
7
Figure 1. General Inputs Timing Diagram
Table 6. Switching Characteristics—General Inputs
(VA, VD = 5 V ±5% or 3.3 V ±10%,TA = 0 to 70°C, CL = 20 pF)
Parameter1
Symbol
Test Condition
Min
Typ
Max
Unit
Cycle Time, MCLK
tmc
16.67
ns
MCLK Duty Cycle
tdty
40
50
60
%
Rise Time, MCLK
tr
5
ns
Fall Time, MCLK
tf
5
ns
RESET Pulse Width2
trl
250
ns
Rise Time, RESET
tRr
1
s
Notes:
1.
All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VD
0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2.
The minimum RESET pulse width is the greater of 5
s or 10 MCLK cycle times.
tf
tmc
tr
VIH
VIL
trl
MCLK
RESET
tRr
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