參數(shù)資料
型號： SI3056SSI-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 31/94頁
文件大?。?/td> 0K
描述： BOARD EVAL SI3056/SI3018 SSI
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，數(shù)據(jù)采集裝置（DAA）
已用 IC / 零件： Si3056
已供物品： 板，CD
Si3056
Si3018/19/10
Rev. 1.05
37
5.25.2. PLL Lock Times
The Si3056 changes sample rates quickly. However,
lock time varies based on the programming of the clock
generator. The following relationships describe the
boundaries on PLL locking time:
PLL1 lock time < 1 ms
PLL2 lock time 100
s to 1 ms
For
modem
designs,
Silicon
Laboratories
recommends that PLL1 be programmed during
initialization. No further programming of PLL1 is
necessary. The SRC[3:0] register can be programmed
for the required initial sample rate, typically 7200 Hz.
Rate changes are made by writing to SRC[3:0]
(Register 7, bits 3:0).
The final design consideration for the clock generator is
the update rate of PLL1. The following criteria must be
satisfied for the PLLs to remain stable:
where FUP1 is shown in Figure 26.
Figure 26. Update Rate of PLL1
5.26. Digital Interface
The Si3056 has two serial interface modes that support
most standard modem DSPs. The M0 and M1 mode
pins select the interface mode. The key difference
between these two serial modes is the operation of the
FSYNC signal. Table 21 summarizes the serial mode
definitions.
The digital interface consists of a single, synchronous
serial link that communicates both telephony and
control data.
In serial mode 0 or 1, the Si3056 operates as a master,
where the master clock (MCLK) is an input, the serial
data clock (SCLK) is an output, and the frame sync
signal (FSYNC) is an output. The MCLK frequency and
the value of the sample rate control registers 7, 8, and 9
determine the sample rate (Fs). The serial port clock,
SCLK, runs at 256 bits per frame, where the frame rate
is equivalent to the sample rate. See "5.25.Clock
Generation" on page 36 for details on programming
sample rates.
The Si3056 transfers 16- or 15-bit telephony data in the
primary timeslot and 16-bit control data in the secondary
timeslot. Figures 27 and 28 show the relative timing of
the serial frames. Primary frames occur at the frame
rate and are always present. To minimize overhead in
the external DSP, secondary frames are present only
when requested.
Two methods exist for requesting a secondary frame to
transfer control information. The default powerup mode
uses the LSB of the 16-bit transmit (TX) data word as a
flag to request a secondary transfer. Only 15-bit TX data
is transferred, which results in a small loss of SNR but
FUP1
FMCLK
N
-------------------
=
144 kHz
≥
DIV
8-bit
PLL1
DIV
N2
DIV
3
DIV
16
PLL2
DIV
8-bit
DIV
M2
Decoder
1
0
01
SCLK
F
UP1
98.304 MHz
32.768 MHz
N1
M1
Slave
SRATE
MCLK
Table 21. Serial Modes
Mode
M1 M0
Description
0
0 0
FSYNC frames data
1
0 1
FSYNC pulse starts data frame
2
1 0
Slave mode
3
1 1
Reserved
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