參數(shù)資料
型號: SI3056SSI-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 4/94頁
文件大?。?/td> 0K
描述: BOARD EVAL SI3056/SI3018 SSI
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,數(shù)據(jù)采集裝置(DAA)
已用 IC / 零件: Si3056
已供物品: 板,CD
Si3056
Si3018/19/10
12
Rev. 1.05
Figure 4. Serial Interface Timing Diagram (DCE = 1, FSD = 0)
Table 8. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 0)
(VA = Charge Pump, VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL =20 pF)
Parameter1,2
Symbol
Min
Typ
Max
Unit
Cycle Time, SCLK
tc
244
1/256 Fs
ns
SCLK Duty Cycle
tdty
—50
%
Delay Time, SCLK
↑ to FSYNC↑
td1
——
20
ns
Delay Time, SCLK
↑ to FSYNC↓
td2
——
20
ns
Delay Time, SCLK
↑ to SDO valid
td3
——
20
ns
Delay Time, SCLK
↑ to SDO Hi-Z
td4
——
20
ns
Delay Time, SCLK
↑ to FSD↓
td5
——
20
ns
Delay Time, SCLK
↑ to FSD↑
td6
——
20
ns
Setup Time, SDO Before SCLK
tsu
25
ns
Hold Time, SDO After SCLK
th
20
ns
Notes:
1.
All timing is referenced to the 50% level of the waveform. Input test levels are VIH =VD – 0.4 V, VIL =0.4 V.
2.
SCLK
FSYNC
(mode 1)
tc
td1
td2
FSYNC
(mode 0)
td2
td6
td2
SDO
(master)
FSYNC
(Mode 0)
SDO
(slave 1)
td3
D15
D14
D13
D0
tsu
th
td4
td3
D15
td5
SDI
D15
D0
D14
th
tsu
td5
FSYNC
(Mode 1)
32 SCLKs
16 SCLKs
D13
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