參數(shù)資料
型號: SI3211PPTX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 119/148頁
文件大?。?/td> 0K
描述: BOARD EVAL W/DISCRETE INTERFACE
標準包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3211
已供物品: 板,CD
Si3210/Si3211
72
Rev. 1.61
Not
Recommended
fo
r N
ew
D
esi
gn
s
Reset settings = 0000_1000
Register 10. Two-Wire Impedance Synthesis Control
Bit
D7D6D5D4D3D2
D1D0
Name
CLC[1:0]
TISE
TISS[2:0]
Type
R/W
Bit
Name
Function
7:6
Reserved
Read returns zero.
5:4
CLC[1:0]
Line Capacitance Compensation.
00 = Off
01 = 4.7 nF
10 = 10 nF
11 = Reserved
3TISE
Two-Wire Impedance Synthesis Enable.
0 = Two-wire impedance synthesis disabled.
1 = Two-wire impedance synthesis enabled.
2:0
TISS[2:0]
Two-Wire Impedance Synthesis Selection.
000 = 600
001 = 900
010 = 600
+ 2.16 F
011 = 900
+ 2.16 F
100 = CTR21 (270
+ 750 || 150 nF)
101 = Australia/New Zealand #1 (220
+ 820 || 120 nF)
110 = Slovakia/Slovenia/South Africa (220
+ 820 || 115 nF)
111 = New Zealand #2 (370
+ 620 || 310 nF)
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