參數(shù)資料
型號: SI3211PPTX-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 45/148頁
文件大?。?/td> 0K
描述: BOARD EVAL W/DISCRETE INTERFACE
標(biāo)準(zhǔn)包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3211
已供物品: 板,CD
Si3210/Si3211
Rev. 1.61
139
Not
Recommended
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ew
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esi
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8.3.2. PCB Land Pattern: 16-Pin ESOIC
Figure 38 illustrates the recommended land pattern for the Si3201 SOIC-16 package. Table 53 lists the values for
the dimensions shown in the illustration.
Figure 38. SOIC-16 PCB Land Pattern Drawing
Table 53. SOIC-16 PCB Land Pattern Dimensions
Dimension
Feature
Min
Max
C1
Pin pad column spacing
5.30
5.40
E
Pin pad row pitch
1.27 BSC
X1
Pin pad width
0.50
0.60
Y1
Pin pad length
1.45
1.55
X2
Thermal pad width
2.20
2.30
Y2
Thermal pad length
3.50
3.60
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X175-17N.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60
m minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
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