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參數(shù)資料
| 型號： | SI5316-C-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 1/26頁 |
| 文件大小： | 0K |
| 描述： | IC PREC JITTER ATTENUATOR 36-QFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 系列： | DSPLL® |
| 類型： | 時鐘振動衰減器 |
| PLL： | 帶旁路 |
| 輸入： | 時鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 710MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 36-QFN（6x6） |
| 包裝： | 托盤 |
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Rev. 1.0 7/12
Copyright 2012 by Silicon Laboratories
Si5316
P RECISION C LOCK J ITTER A TTENUATOR
Features
Applications
Description
The Si5316 is a low jitter, precision jitter attenuator for high-speed
communication systems, including OC-48, OC-192, 10G Ethernet, and
10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38,
77, 155, 311, or 622 MHz frequency range and generates a jitter-
attenuated clock output at the same frequency. Within each of these clock
ranges, the device can be tuned approximately 15% higher than nominal
SONET/SDH frequencies, up to a maximum of 710 MHz in the 622 MHz
range. The Si5316 is based on Silicon Laboratories' 3rd-generation
DSPLL technology, which provides any-frequency synthesis and jitter
attenuation in a highly integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The DSPLL loop bandwidth is
digitally programmable, providing jitter performance optimization at the
application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the
Si5316 is ideal for providing jitter attenuation in high performance timing
applications.
Fixed frequency jitter attenuator
with selectable clock ranges at
19, 38, 77, 155, 311, and
622 MHz (710 MHz max)
Support for SONET, 10GbE,
10GFC, and corresponding FEC
rates
Ultra-low jitter clock output with
jitter generation as low as
0.3 psRMS (50 kHz–80 MHz)
Integrated loop filter with
selectable loop bandwidth
(100 Hz–7.9 kHz)
Meets OC-192 GR-253-CORE
jitter specifications
Dual clock inputs with integrated
clock select mux
One clock input can be 1x, 4x, or
32x the frequency of the second
clock input
Single clock output with
selectable signal format:
LVPECL, LVDS, CML, CMOS
LOL, LOS alarm outputs
Pin programmable settings
On-chip voltage regulator for 1.8
±5%, 2.5 ±10%, or 3.3 V ±10%
operation
Small size (6 x 6 mm 36-lead
QFN)
Pb-free, RoHS compliant
Optical modules
SONET/SDH OC-48/OC-192/
STM-16/STM-64 line cards
10GbE, 10GFC line cards
ITU G.709 line cards
Wireless basestations
Test and measurement
Synchronous Ethernet
Patents pending
Ordering Information:
See page 20.
Pin Assignments
1
2
3
29
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
NC
RST
C2B
C1B
GND
VDD
XA
VD
D
RATE0
CK
IN
2
+
CKIN2–
DBL_B
Y
RATE1
CKIN1+
CKIN1–
CS
BWSEL0
BWSEL1
FRQSEL
CK1DIV
CK2DIV
NC
SFO
U
T1
GND
VDD
SF
OUT
0
CKOUT
–
CKOUT
+
NC
GND
Pad
FRQSEL0
GND
9
18
19
28
XB
LO
L
GND
NC
Si5316
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5316-C-GMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Pin-Ctrl Precision Jitt Attn 2In/1Out RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5316-EVB | 功能描述:時鐘和定時器開發(fā)工具 Si5316 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5317 | 制造商:SILABS 制造商全稱:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
| Si5317A-C-GM | 功能描述:標(biāo)準(zhǔn)時鐘振蕩器 Pin-Program. Jitter Cleaning Clock RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列: |
| SI5317A-C-GMR | 功能描述:時鐘合成器/抖動清除器 Pin-Program Jitter Clean Clk 1In/2Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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