參數(shù)資料
型號: SI5316-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 8/26頁
文件大小: 0K
描述: IC PREC JITTER ATTENUATOR 36-QFN
標(biāo)準(zhǔn)包裝: 490
系列: DSPLL®
類型: 時(shí)鐘振動(dòng)衰減器
PLL: 帶旁路
輸入: 時(shí)鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 710MHz
除法器/乘法器: 是/無
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
Si5316
16
Rev. 1.0
5. Pin Descriptions: Si5316
Table 8. Si5316 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
1
RST
ILVCMOS
External Reset.
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state. Clock outputs are tristated
during reset. After rising edge of RST signal, the Si5316 will perform
an internal self-calibration when a valid signal is present.
This pin has a weak pull-up.
2, 9, 28,
29, 36
NC
No Connection.
Leave floating. Make no external connection to this pin for normal
operation.
3C1B
O
LVCMOS
CKIN1 Loss of Signal.
Active high Loss-of-signal indicator for CKIN1. Once triggered, the
alarm will remain active until CKIN1 is validated.
0 = CKIN1 present
1 = LOS on CKIN1
4C2B
O
LVCMOS
CKIN2 Loss of Signal.
Active high Loss-of-signal indicator for CKIN2. Once triggered, the
alarm will remain active until CKIN2 is validated.
0 = CKIN2 present
1 = LOS on CKIN2
5, 10, 32
VDD
Supply
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capac-
itors should be associated with the following VDD pins:
5
0.1 F
10
0.1 F
32
0.1 F
A 1.0 F should also be placed as close to device as is practical.
*Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD).
1
2
3
29
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
NC
RST
C2B
C1B
GND
VDD
XA
VDD
RA
T
E
0
CKIN2+
CK
IN
2–
DB
L_B
Y
RA
T
E
1
CKIN1+
CK
IN
1–
CS
BWSEL0
BWSEL1
FRQSEL1
CK1DIV
CK2DIV
NC
SF
O
U
T
1
GN
D
VDD
SF
O
U
T
0
CKO
U
T
CKO
U
T
+
NC
GND
Pad
FRQSEL0
GND
9
18
19
28
XB
LO
L
GND
NC
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