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參數(shù)資料
| 型號(hào)： | SI5316-C-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 9/26頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PREC JITTER ATTENUATOR 36-QFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 系列： | DSPLL® |
| 類型： | 時(shí)鐘振動(dòng)衰減器 |
| PLL： | 帶旁路 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 710MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 36-QFN（6x6） |
| 包裝： | 托盤 |
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Si5316
Rev. 1.0
17
7
6
XB
XA
IAnalog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to Family Reference Manual for
interfacing to an external reference. External reference must be
from a high-quality clock source (TCXO, OCXO). Frequency of crys-
tal or external clock is set by the RATE pins.
8, 19,
20, 31
GND
Supply
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. Grounding these
pins does not eliminate the requirement to ground the GND PAD on
the bottom of the package.
Pins 19 and 20 may be left NC.
11
15
RATE0
RATE1
I
3-Level*
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crystal or
reference clock to be applied to the XA/XB port. Refer to the Family
Reference Manual for settings. These pins have both a weak pull-up
and a weak pull-down; they default to M. The "HH" setting is not
supported.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
12
13
CKIN2+
CKIN2–
IMulti
Clock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal.
14
DBL_BY
I
3-Level*
Output Disable/Bypass Mode Control.
Controls enable of CKOUT divider/output buffer path and PLL
bypass mode.
L = CKOUT enabled
M = CKOUT disabled
H = Bypass mode with CKOUT enabled
This pin has a weak pull-up and weak pull-down and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state. Bypass mode is not sup-
ported for CMOS clock outputs.
16
17
CKIN1+
CKIN1–
IMulti
Clock Input 1.
Differential input clock. This input can also be driven with a single-
ended signal.
18
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator.
0 = PLL locked
1 = PLL unlocked
Table 8. Si5316 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5316-C-GMR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Pin-Ctrl Precision Jitt Attn 2In/1Out RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5316-EVB | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Si5316 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5317 | 制造商:SILABS 制造商全稱:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
| Si5317A-C-GM | 功能描述:標(biāo)準(zhǔn)時(shí)鐘振蕩器 Pin-Program. Jitter Cleaning Clock RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列: |
| SI5317A-C-GMR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Pin-Program Jitter Clean Clk 1In/2Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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