參數(shù)資料
型號(hào)： SI5316-C-GM
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 7/26頁(yè)
文件大?。?/td> 0K
描述： IC PREC JITTER ATTENUATOR 36-QFN
標(biāo)準(zhǔn)包裝： 490
系列： DSPLL®
類(lèi)型： 時(shí)鐘振動(dòng)衰減器
PLL： 帶旁路
輸入： 時(shí)鐘
輸出： CML，CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 710MHz
除法器/乘法器： 是/無(wú)
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 36-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 36-QFN（6x6）
包裝： 托盤(pán)
Si5316
Rev. 1.0
15
4. Functional Description
The Si5316 is a precision jitter attenuator for high-speed
communication systems, including OC-48/STM-16, OC-
192/STM-64, 10G Ethernet, and 10G Fibre Channel.
The Si5316 accepts dual clock inputs in the 19, 38, 77,
155, 311, or 622 MHz frequency range and generates a
jitter-attenuated clock output at the same frequency.
Within each of these clock ranges, the device can be
tuned approximately 15% higher than nominal SONET/
SDH frequencies, up to a maximum of 710 MHz in the
622 MHz range. The Si5316 is based on Silicon
Laboratories' 3rd-generation DSPLL technology, which
provides any-frequency synthesis and jitter attenuation
in a highly integrated PLL solution that eliminates the
need for external VCXO and loop filter components. For
applications which require input clocks at different
frequencies, the frequency of CKIN1 can be 1x, 4x, or
32x the frequency of CKIN2 as specified by the CK1DIV
and CK2DIV inputs.
The Si5316 PLL loop bandwidth is selectable via the
BWSEL[1:0] pins and supports a range from 100 Hz to
7.9 kHz. To calculate potential loop bandwidth values
for a given input/output clock
frequency, Silicon
Laboratories
offers
a
PC-based
software
utility,
DSPLLsim, that calculates valid loop bandwidth settings
automatically. This utility can be downloaded from http://
www.silabs.com/timing.
The
Si5316
supports
manual
active
input
clock
selection. The Si5316 monitors both input clocks for
loss-of-signal and provides a LOS alarm when it detects
missing pulses on either input clock. Hitless switching is
not supported by the Si5316. During a clock transition,
the phase of the output clock will slew at a rate defined
by the PLL loop bandwidth until the original input clock
phase to output clock phase is restored. The device
monitors the lock status of the PLL. The lock detect
algorithm works by continuously monitoring the phase
of the input clock in relation to the phase of the
feedback clock.
The Si5316 has one differential clock output. The
electrical format of the clock output is programmable to
support LVPECL, LVDS, CML, or CMOS loads. For
system-level debugging, a bypass mode is available
which drives the output clock directly from the input
clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
4.1. External Reference
An
external,
38.88 MHz
clock
or
a
low-cost
114.285 MHz 3rd overtone crystal is used as part of a
fixed-frequency oscillator within
the
DSPLL. This
external reference is required for the device to operate.
Silicon Laboratories recommends using a high quality
crystal. Specific recommendations may be found in the
Family Reference Manual. An external 38.88 MHz clock
from a high quality OCXO or TCXO can also be used as
a reference for the device.
In digital hold, the DSPLL remains locked to this
external reference. Any changes in the frequency of this
reference when the DSPLL is in digital hold will be
tracked by the output of the device. Note that crystals
can have temperature sensitivities.
4.2. Further Documentation
Consult
the
Silicon
Laboratories
Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5316. Additional design
support is available from Silicon Laboratories through
your distributor.
Silicon
Laboratories
has
developed
a
PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing.
相關(guān)PDF資料
PDF描述
AD7839ASZ IC DAC 13BIT OCTAL V-OUT 44-MQFP
AD5360BSTZ IC DAC 16BIT 16CH SERIAL 52-LQFP
AD5764BSUZ IC DAC 16BIT QUAD VOUT 32-TQFP
VE-J53-MZ-F4 CONVERTER MOD DC/DC 24V 25W
AD7568BSZ IC DAC 12BIT OCTAL LC2MOS 44MQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5316-C-GMR 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Pin-Ctrl Precision Jitt Attn 2In/1Out RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
Si5316-EVB 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 Si5316 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類(lèi)型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
SI5317 制造商:SILABS 制造商全稱:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock
Si5317A-C-GM 功能描述:標(biāo)準(zhǔn)時(shí)鐘振蕩器 Pin-Program. Jitter Cleaning Clock RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類(lèi)型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列:
SI5317A-C-GMR 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Pin-Program Jitter Clean Clk 1In/2Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*