參數(shù)資料
型號(hào)： SI5338L-A-GM
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 19/44頁(yè)
文件大?。?/td> 0K
描述： IC CLK GEN I2C BUS PROG 24QFN
標(biāo)準(zhǔn)包裝： 490
系列： MultiSynth™
類(lèi)型： *
PLL： 是
輸入： CML，HCSL，HSCL，LVDS，LVPECL，晶體
輸出： CMOS，HCSL. HSTL. LVDS. LVPECL. SSTL
電路數(shù)： 1
比率 - 輸入:輸出： 1:4
差分 - 輸入:輸出： 是/是
頻率 - 最大： 350MHz
除法器/乘法器： 是/是
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 24-QFN（4x4）
包裝： 托盤(pán)
Si5338
26
Rev. 1.3
3.9. Reset Options
There are two types of resets on the Si5338, POR and
soft reset. A POR reset automatically occurs whenever
the supply voltage on the VDD is applied.
The soft reset is forced by writing 0x02 to register 246.
This bit is not self-clearing, and thus it may read back as
a 1 or a 0. A soft reset will not download any pre-
programmed NVM and will not change any register
values in RAM.
The soft reset performs the following sequence:
1. All outputs turn off except if programmed to be
always on.
2. Internal calibrations are done and MultiSynths are
initialized.
a. Outputs that are synchronous are phase
aligned (if Rn = 1).
3. 25 ms is allowed for the PLL to lock (no delay occurs
when FCAL_OVRD_EN = 1).
4. Turn on all outputs that were turned off in step 1.
3.10. Features of the Si5338
The Si5338 offers several features and functions that
are useful in many timing applications. The following
paragraphs describe in detail the main features and
typical applications. All of these features can be easily
configured using the ClockBuilder Desktop. See "3.1.1.
3.10.1. Frequency Increment/Decrement
Each
of
the
output
clock
frequencies
can
be
independently stepped up or down in predefined steps
as low as 1 ppm per step and with a resolution of
1 ppm. Setting of the step size and control of the
frequency increment or decrement is accomplished
through the I2C interface. Alternatively, the Si5338 can
be ordered with optional frequency increment (FINC)
and
frequency
decrement
(FDEC)
pins
for
pin-
controlled applications. Note that FINC and FDEC pins
only affect CLK0. Frequency increment and decrement
of all other channels must be performed by I2C writes to
the appropriate registers. See Table 17 on page 36 for
ordering information of pin-controlled devices. When
phase is decremented, the MultiSynth output clock edge
will happen sooner which will create a single half cycle
that is shorter than expected for the MultiSynth output
clock frequency. Care must be taken to insure that a
single phase decrement does not produce a half cycle
that is less than 4/fvco or an unwanted glitch in the
MultiSynth output may occur.
The frequency increment and decrement feature is
useful
in
applications
requiring
a
variable
clock
frequency (e.g., CPU speed control, FIFO overflow
management, etc.) or in applications where frequency
margining (e.g., fout ±5%) is necessary for design
verification
and
manufacturing
test.
Frequency
increment or decrement can be applied as fast as
1.5 MHz when it is done by pin control. When under I2C
control, the frequency increment and decrement update
rate is limited by the I2C bus speed. The magnitude of
the frequency step has 0 ppm error. Frequency steps
are seamless and glitchless.
If a frequency increment/decrement command causes
the
MultiSynth
output
frequency
to
exceed
the
maximum/minimum limits, then a glitch on the output is
likely to occur. The max frequency of a MultiSynth
output that is using frequency increment/decrement is
Fvco/8, and the minimum frequency is 5 MHz.
3.10.2. Output Phase Increment/Decrement
The Si5338 has a digitally-controlled glitchless phase
increment and decrement feature that allows adjusting
the phase of each output clock in relation to the other
output clocks. The phase of each output clock can be
adjusted with an accuracy of 20 ps over a range of
±45 ns. Setting of the step size and control of the phase
increment or decrement is accomplished through the
I2C interface. Alternatively, the Si5338 can be ordered
with optional phase increment (PINC) and phase
decrement (PDEC) pins for pin-controlled applications.
In pin controlled applications the phase increment and
decrement update rate is as fast as 1.5 MHz. In I2C
applications, the maximum update rate is limited by the
speed of the I2C. See Table 17 for ordering information
of pin-controlled devices. When phase is decremented,
the MultiSynth output clock edge will happen sooner,
which will create a single half cycle that is shorter than
expected for the MultiSynth output clock frequency.
Care must be taken to insure that a single phase
decrement does not produce a half cycle that is less
than 4/fvco or an unwanted glitch in the MultiSynth
output may occur.
The phase increment and decrement feature provides a
useful method for fine tuning setup and hold timing
margins or adjusting for mismatched PCB trace lengths.
3.10.3. Programmable Initial Phase Offset
Each output clock can be set for its initial phase offset
up to ±45 ns. In order for the initial phase offset to be
applied correctly at power up, the VDDOx output supply
voltage must cross 1.2 V before the VDD (pins 7,24)
core power supply voltage crosses 1.45 V. This applies
to the each driver output individually. A soft_reset will
also guarantee that the programmed Initial Phase Offset
is applied correctly. The initial phase offset only works
on outputs that have their R divider set to 1.
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