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參數(shù)資料
| 型號： | SI5338L-A-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 9/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN I2C BUS PROG 24QFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 系列： | MultiSynth™ |
| 類型： | * |
| PLL： | 是 |
| 輸入： | CML，HCSL，HSCL，LVDS，LVPECL，晶體 |
| 輸出： | CMOS，HCSL. HSTL. LVDS. LVPECL. SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 350MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN（4x4） |
| 包裝： | 托盤 |
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Si5338
Rev. 1.3
17
3. Functional Description
Figure 1. Si5338 Block Diagram
3.1. Overview
The Si5338 is a high-performance, low-jitter clock
generator capable of synthesizing four independent
user-programmable clock frequencies up to 350 MHz
and select frequencies up to 710 MHz. The device
supports free-run operation using an external crystal, or
it can lock to an external clock for generating
synchronous clocks. The output drivers support four
differential clocks or eight single-ended clocks or a
combination of both. The output drivers are configurable
to support common signal formats, such as LVPECL,
LVDS, HCSL, CMOS, HSTL, and SSTL. Separate
output supply pins allow supply voltages of 3.3, 2.5, 1.8,
and 1.5 V to support the multi-format output driver. The
core voltage supply accepts 3.3, 2.5, or 1.8 V and is
independent from the output supplies.
Using its two-stage synthesis architecture and patented
high-resolution MultiSynth technology, the Si5338 can
generate four independent frequencies from a single
input frequency. In addition to clock generation, the
inputs can bypass the synthesis stage enabling the
Si5338 to be used as a high-performance clock buffer or
a combination of a buffer and generator.
For applications that need fine frequency adjustments,
such as clock margining, each of the synthesized
frequencies can be incremented or decremented in
user-defined steps as low as 1 ppm per step.
Output-to-output phase delays are also adjustable in
user-defined
steps
with
an
error
of
<20 ps
to
compensate for PCB trace delays or for fine tuning of
setup and hold margins.
A zero-delay mode is also available to help minimize
input-to-output delay. Spread spectrum is available on
each of the clock outputs for EMI-sensitive applications,
such as PCI Express.
Configuration and control of the Si5338 is mainly
handled
through
the
I2C/SMBus
interface.
Some
features, such as output enable and frequency or phase
adjustments, can optionally be pin controlled. The
device has a maskable interrupt pin that can be
monitored for loss of lock or loss of input signal
conditions.
The device also provides the option of storing a user-
definable clock configuration in its non-volatile memory
(NVM), which becomes the default clock configuration
at power-up.
3.1.1. ClockBuilder Desktop Software
To simplify device configuration, Silicon Labs provides
ClockBuilder Desktop software, which can operate
stand alone or in conjunction with the Si5338 EVB.
When the software is connected to an Si5338 EVB it will
control both the supply voltages to the Si5338 as well as
the entire clock path within the Si5338. Clockbuilder
Desktop can also measure the current delivered by the
EVB regulators to each supply voltage of the Si5338. A
Si5338 configuration can be written to a text file to be
used by any system to configure the Si5338 via I2C.
ClockBuilder
Desktop
can
be
downloaded
from
www.silabs.com/ClockBuilder and runs on Windows XP,
Windows Vista, and Windows 7.
Phase
Frequency
Detector
Loop
Filter
VCO
CLK0A
÷P2
VDDO1
VDDO2
VDDO3
VDDO0
MultiSynth
÷M0
I2C_LSB/PDEC/FDEC
OEB/PINC/FINC
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
÷P1
IN3
IN2
IN1
÷R1
MultiSynth
÷M1
MultiSynth
÷M2
MultiSynth
÷M3
IN6
IN4
IN5
Osc
MultiSynth
÷N
Control
NVM
(OTP)
÷R0
÷R2
÷R3
Input
Stage
Synthesis
Stage 1
(PLL)
Synthesis
Stage 2
Output
Stage
CLKIN
Control & Memory
SCL
SDA
INTR
VDD
ref
fb
RAM
FDBK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5338L-A-GMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C-Program Clk Gen 0.16-350MHz Pin-Ctrl RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5338L-B00400-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338L-B00400-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338L-B02376-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube |
| Si5338L-B-GM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C-PRGRMBL clock generatr 0.16-350MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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