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參數(shù)資料
| 型號： | SI5338N-A00000-GMR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件頁數(shù)： | 11/34頁 |
| 文件大小： | 285K |
| 代理商： | SI5338N-A00000-GMR |
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Si5338
Rev. 0.5
19
3.5.2. Configuring the Si5338 by Writing to NVM
An alternative to writing the device configuration to RAM
after every power cycle is to write directly to the NVM.
Writing to NVM only has to be done once and becomes
the default configuration after every power cycle or
POR. Writing to NVM is easily done using the Si5338
field programmer (Si5338-PROG-EVB). NVM is an OTP
memory, so it can only be written once. Alternatively,
parts can be pre-ordered with a custom NVM default
configuration.
3.5.3. Changing the Default Configuration
Once the configuration is stored in RAM it is always
modifiable by directly writing to individual registers. An
example could be selecting a new reference input,
configuring a new output frequency, etc. A full Si5338
software register map is available from the Silicon Labs
web site. The register map of the Si5338 is addressable
as two memory pages each containing 256 8-bit
registers as shown in Figure 8. For more information on
configuring the Si5338, please refer to application note
AN411.
Figure 8. Si5338 Memory Map (RAM)
3.6. Status Indicators
An interrupt pin (INTR) is available to indicate a loss of
signal (LOS) condition, a APLL loss of lock (LOL)
condition, or that the APLL is in process of acquiring
lock (SYS_CAL). As shown in Figure 9, a status register
at address 218 is available to help identify the exact
event that caused the interrupt pin to become active.
Figure 9. Status Register
The INTR pin provides a useful status indicator for
systems that have access to the I2C interface, and for
systems that do not. Figure 10 shows a typical
connection with the required pull-up resistor to VDD.
3.6.1. Using the INTR pin in Systems with I2C
For systems that use the I2C interface for system
monitoring, the INTR pin provides a convenient fault
indicator for a processor. Once the interrupt pin
becomes active, the processor can identify its trigger by
reading the status register. Each of the status bits can
be individually masked to prevent them from causing an
interrupt. The status mask register is located at address
6.
3.6.2. Using the INTR pin in Systems without I2C
The INTR pin also provides a useful function in systems
that require a pin controlled fault indicator. Pre-setting
the interrupt mask register allows the INTR pin to
become an indicator for a specific event such as LOS
and/or LOL. Therefore the INTR pin can be used to
indicate a single fault event, or even multiple events.
Figure 10. INTR pin with required pull-up
Page 0
0
255
Input
Configuration
MultiSynth
Configuration
Device Control
and Status
PLL
Configuration
Output
Configuration
Frequency Inc/Dec
Configuration
Page Select
Page 1
(256)
(512)
(347)
Reserved
Spread Spectrum
Configuration
218
System Calibration
(Lock Acquisition)
Sys
Cal
0
LOS
Clk
LOS
Fdbk
LOL
1
2
3
4
5
6
7
Loss Of Signal
Clock Input
Loss Of Signal
Feedback Input
Loss Of Lock
INTR
VDD
1k
Control
NVM
(OTP)
Control & Memory
RAM
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5338N-A00211-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
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| SI5338N-A01659-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| Si5338N-A-GM | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C-prgrmmbl clock generatr .16-700 MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5338N-A-GMR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C Program Clk Gen 0.16-710MHz 4Clk In RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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