參數(shù)資料
型號(hào)： SI5338N-A00000-GMR
廠商： SILICON LABORATORIES
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24
封裝： 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24
文件頁(yè)數(shù)： 16/34頁(yè)
文件大小： 285K
代理商： SI5338N-A00000-GMR
Si5338
Rev. 0.5
23
5. I2C Interface
Configuration an operation of the Si5338 is controlled
by reading and writing to the RAM space using the I2C
interface. The device operates in slave mode with 7-bit
addressing
and
can
operate
in
Standard-Mode
(100 kbps) or Fast-Mode (400 kbps) and supports burst
data transfer with auto address increments.
The I2C bus consists of a bidirectional serial data line
(SDA) and a serial clock input (SCL) as shown in
Figure 19. Both the SDA and SCL pins must be
connected to the VDD supply via an external pull-up as
recommended by the I2C specification.
Figure 19. I2C and Control Signals
The 7-bit device (slave) address of the Si5338 consist of
a 6-bit fixed address plus a user selectable LSB bit as
shown in Figure 20. The LSB bit is selectable using the
optional I2C_LSB pin which is available as an ordering
option for applications that require more than one
Si5338 on a single I2C bus. Devices without the
I2C_LSB pin option have a fixed 7-bit address of 70h as
shown in Figure 20. Other custom I2C addresses are
also possible. See Table 15 for details on device
ordering information with the optional I2C_LSB pin.
Figure 20. Si5338 I2C Slave Address
Data is transferred MSB first in 8-bit words as specified
by the I2C specification. A write command consists of a
7-bit device (slave) address + a write bit, an 8-bit
register address, and 8 bits of data as shown in
Figure 21. A write burst operation is also shown where
every additional data word is written using to an auto-
incremented address.
Figure 21. I2C Write Operation
A read operation is performed in two stages. A data
write is used to set the register address, then a data
read is performed to retrieve the data from the set
address. A read burst operation is also supported. This
is shown in Figure 22.
Figure 22. I2C Read Operation
AC and DC electrical specifications for the SCL and
SDA
pins
are
shown
in
The
timing
specifications and timing diagram for the I2C bus is
compatible with the I2C-Bus Standard. SDA timeout is
supported for compatibility with SMBus interfaces.
The I2C bus can be operated at a bus voltage of 1.71 to
3.63 V and is 3.3 V tolerant.
Control
I2C_LSB
I2C_LSB/PDEC/FDEC
OEB/PINC/FINC
0/1
SCL
SDA
I
2CBus
VDD
Slave Address
(with I2C_LSB Option)
1 1 1 0 0 0 0/1
I2C_LSB pin
0
1
2
3
4
5
6
Slave Address
(without I2C_LSB Option)
1 1 1 0 0 0
0
1
2
3
4
5
6
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
From slave to master
From master to slave
Write Operation – Single Byte
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A Data [7:0]
P
A
Write Operation - Burst (Auto Address Increment)
Reg Addr +1
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A Data [7:0]
P
A
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
From slave to master
From master to slave
Read Operation – Single Byte
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A P
Read Operation - Burst (Auto Address Increment)
Reg Addr +1
S
1 A
Slv Addr [6:0]
Data [7:0]
P
N
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A P
S
1 A
Slv Addr [6:0]
Data [7:0]
A
P
N
Data [7:0]
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SI5338N-A-GMR 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C Program Clk Gen 0.16-710MHz 4Clk In RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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