參數(shù)資料
型號: SI5338N-A00000-GMR
廠商: SILICON LABORATORIES
元件分類: 時鐘產(chǎn)生/分配
英文描述: 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24
封裝: 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24
文件頁數(shù): 31/34頁
文件大?。?/td> 285K
代理商: SI5338N-A00000-GMR
Si5338
6
Rev. 0.5
Table 5. Performance Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
APLL Acquisition Time
tACQ
——
25
ms
APLL Lock Range
fLOCK
5000
ppm
APLL Loop Bandwidth
fBW
—1.6
MHz
MultiSynth Frequency
Synthesis Resolution
fRES
Output frequency < Fvco/8
0
1
ppb
CLKIN Loss of Signal Detect
Time
tLOS
—2.6
5
s
CLKIN Loss of Signal Release
Time
tLOSRLS
0.01
0.2
1
s
APLL Loss of Lock Detect Time
tLOL
Clock multiplication ratio off
by 1000 ppm
—5
10
ms
Reset Time
tRST
——
2
ms
POR to Output Clock Valid
(Pre-programmed Devices)
tRDY
——
2
ms
Input-to-Output Propagation
Delay
tPROP
Buffer Mode
(APLL Bypass)
—2.5
ns
Output-Output Skew
tDSKEW
Outputs at same frequency,
signal format
——
100
ps
Programmable Initial
Phase Offset
POFFSET
–45
+45
ns
Phase Increment/Decrement
Accuracy
PSTEP
——
20
ps
Phase Increment/Decrement
Range
PRANGE
–45
+45
ns
Frequency range for phase
increment/decrement
fPRANGE
——
3501
MHz
Phase Increment/Decrement
Update Rate
PUPDATE
Pin control2,3
1500
kHz
Frequency Increment/
Decrement Step Size
fSTEP
R divider not used
1
See
Note 1
ppm
Notes:
1. Keep MultiSynth output frequency between 5 MHz to Fvco/8.
2. Maximum frequency is Fvco/8.
3. Update rate via I2C is limited by the time it takes to perform a write operation.
4. Default value is.5% down spread.
5. Default value is ~31.5 kHz
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