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參數(shù)資料
| 型號： | SI5350B-A-GT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 4/24頁 |
| 文件大小： | 0K |
| 描述： | IC CLK GEN PLL BLANK CUST 10MSOP |
| 標準包裝： | 50 |
| 系列： | MultiSynth™ |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 133MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.25 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
Si5350B
12
Rev. 0.9
Figure 6. Available Spread Spectrum Profiles
4.2.3. Invert/Non-Invert
By default, each of the output clocks are generated in phase (non-inverted) with respect to each other. An option to
invert any of the clock outputs is also available.
4.2.4. Output State When Disabled
There are up to three output enable pins configurable on the Si5350B as described in “5. Pin Descriptions (20-
QFN, 24-QSOP)” . The output state when disabled for each of the outputs is configurable as one of the following:
disable low, disable high, or disable in high-impedance.
4.2.5. Powering Down Unused Outputs
Unused clock outputs can be completely powered down to conserve power.
4.3. Programmable Control Pins (P0–P3) Options
Up to four programmable control pins (P0-P3) are configurable allowing direct pin control of the following features:
4.3.1. Spread Spectrum Enable (SSEN)
An optional control pin allows disabling the spread spectrum feature for all outputs that were configured with
spread spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient
method of evaluating the effect of using spread spectrum clocks during EMI compliance testing.
4.3.2. Frequency Select (FS_0, FS_1)
The Si5350B offers the option of configuring up to two frequencies per clock output (CLK0-CLK5) for either free-
running or synchronous clocks. This is a useful feature for applications that need to support more than one free-
running or synchronous clock rate on the same output. An example of this is shown in Figure 7. The FS pins select
which frequency is generated from the clock output. In this example FS0 select the output frequency on CLK0, and
FS1 selects the frequency on CLK1.
Figure 7. Example of Generating Two Clock Frequencies from the Same Clock Output
fc
R educed
Am plitude
and E M I
Down S pread
fc
No Spread
Spectrum
Center
Frequency
Am plitude
74.25 MHz or
74.25
1.001
MHz
27 MHz
XA
XB
CLK0
FS0
Si5350B
Free-running Clock
FS1
VC
24.576 MHz or 22.5792 MHz
CLK1
Synchronous Clock
Video/Audio
Processor
Free-running Frequency
FS0
Bit Level
0
1
74.25 MHz
F1_0:
F2_0:
74.25
1.001
MHz
Synchronous Frequency
FS1
Bit Level
0
1
24.576 MHz
F1_1:
F2_1:
22.5792 MHz
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參數(shù)描述 |
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| SI5350B-A-GTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate Dual PLL 133MHz Clk VCXO RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5350B-A-GU | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 AnyRate 2 PLL 125MHz Clk w/VCXO 8 outputs RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5350B-A-GUR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate Dual PLL 133MHz Clk VCXO RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5350B-Axxxxx-GM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 133MHz Clock with VCXO , 8 outputs, 20-QFN (customized) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5350B-Axxxxx-GT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 133MHz Clock with VCXO , 3 outputs, 10-MSOP (customized) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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