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參數(shù)資料
| 型號： | SI5350B-A-GT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN PLL BLANK CUST 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 系列： | MultiSynth™ |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 133MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.25 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
Si5350B
14
Rev. 0.9
4.3.4. Power Down (PDN)
An optional power down control pin allows a full shutdown of the Si5350B to minimize power consumption when its
output clocks are not being used. The Si5350B is in normal operation when the PDN pin is held low and is in power
down mode when held high. Power consumption when the device is in power down mode is indicated in Table 2 on
4.4. Voltage Control Input (VC)
The VCXO architecture of the Si5350B eliminates the need for an external pullable crystal. Only a standard, low-
cost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.
The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the
VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90% of VDD), and
reliable startup and operation. Refer to Table 3 on page 5 for VCXO specification details.
A unique feature of the Si5350B is its ability to generate multiple output frequencies controlled by the same control
voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same
reference. An example is illustrated in Figure 10.
Figure 10. Generating One Or More Synchronous Clocks
4.4.1. Control Voltage Gain (kV)
The voltage level on the VC pin directly controls the output frequency. The rate of change in output clock frequency
(kv) is configurable from 18 ppm/V up to 150 ppm/V. This allows a configurable pull range from ±30 ppm to
A key advantage of the VCXO design in the Si5350B is its highly linear tuning range. This allows better control of
PLL stability and jitter performance over the entire control voltage range.
CLK0
VC
Multi
Synth
2
CLK1
CLK2
Additional MultiSynths can be
added to generate multiple
synchronous clocks with
different output frequencies
XA
XB
OSC
VCXO
Multi
Synth
0
Multi
Synth
1
Control
Voltage
Fixed Frequency
Crystal (non-pullable)
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參數(shù)描述 |
|---|---|
| SI5350B-A-GTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate Dual PLL 133MHz Clk VCXO RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5350B-A-GU | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 AnyRate 2 PLL 125MHz Clk w/VCXO 8 outputs RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5350B-A-GUR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate Dual PLL 133MHz Clk VCXO RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5350B-Axxxxx-GM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 133MHz Clock with VCXO , 8 outputs, 20-QFN (customized) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5350B-Axxxxx-GT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 133MHz Clock with VCXO , 3 outputs, 10-MSOP (customized) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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