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參數(shù)資料
| 型號： | SJA1000 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Stand-alone CAN controller(單機CAN控制器) |
| 中文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 20/68頁 |
| 文件大?。?/td> | 234K |
| 代理商： | SJA1000 |
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2000 Jan 04
20
Philips Semiconductors
Product specification
Stand-alone CAN controller
SJA1000
6.3.9.1
Acceptance Code Register (ACR)
Table 8
ACR bit allocation; can address 4
BIT 7
AC.7
BIT 6
AC.6
BIT 5
AC.5
BIT 4
AC.4
BIT 3
AC.3
BIT 2
AC.2
BIT 1
AC.1
BIT 0
AC.0
This register can be accessed (read/write), if the reset
request bit is set HIGH (present). When a message is
received which passes the acceptance test and there is
receive buffer space left, then the respective descriptor
and data field are sequentially stored in the RXFIFO.
When the complete message has been correctly received
the following occurs:
The receive status bit is set HIGH (full)
If the receive interrupt enable bit is set HIGH (enabled),
the receive interrupt is set HIGH (set).
The acceptance code bits (AC.7 to AC.0) and the eight
most significant bits of the message’s identifier
(ID.10 to ID.3) must be equal to those bit positions which
are marked relevant by the acceptance mask bits
(AM.7 to AM.0). If the conditions as described in the
following equation are fulfilled, acceptance is given:
(ID.10 to ID.3)
≡
(AC.7 to AC.0)]
∨
(AM.7 to AM.0)
≡
11111111
6.3.9.2
Acceptance Mask Register (AMR)
Table 9
AMR bit allocation; CAN address 5
BIT 7
AM.7
BIT 6
AM.6
BIT 5
AM.5
BIT 4
AM.4
BIT 3
AM.3
BIT 2
AM.2
BIT 1
AM.1
BIT 0
AM.0
This register can be accessed (read/write), if the reset
request bit is set HIGH (present). The acceptance mask
register qualifies which of the corresponding bits of the
acceptance code are ‘relevant’ (AM.X = 0) or ‘don’t care’
(AM.X = 1) for acceptance filtering.
6.3.9.3
Other registers
The other registers are described in Section 6.5.
6.4
PeliCAN mode
6.4.1
P
ELI
CAN
ADDRESS LAYOUT
The CAN controller’s internal registers appear to the CPU
as on-chip memory mapped peripheral registers. Because
the CAN controller can operate in different modes
(operating/reset; see also Section 6.4.3), one has to
distinguish between different internal address definitions.
Starting from CAN address 32 the complete internal RAM
(80-byte) is mapped to the CPU interface.
相關(guān)PDF資料 |
PDF描述 |
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| SJE1349 | NPN PLASTIC POWER TRANSISTOR |
| SK016R | SCRs |
| SK006V | SCRs |
| SK008D | Box-shaped pin header, Discrete wire crimping connection, Discrete wire connectors; HRS No: 543-0505-6 00; No. of Positions: 12; Connector Type: Wire; Contact Gender: Female; Contact Spacing (mm): 2; Terminal Pitch (mm): 2; Current Rating(Amps)(Max.): 2; Operating Temperature Range (degrees C): -30 to 85; General Description: Housing; For Discrete wire; Crimping |
| SK008L | SCRs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SJA1000/N1,112 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC STAND-ALONE CAN CONTROLLER RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| SJA1000/N1112 | 制造商:NXP Semiconductors 功能描述:IC CAN CONTROLLER 1000 DIP28 |
| SJA1000N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Stand-alone CAN controller |
| SJA1000T | 制造商:NXP Semiconductors 功能描述: |
| SJA1000T/N,112 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC STAND ALONE CAN CONTROLLER RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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