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參數(shù)資料
| 型號： | SJA1000 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Stand-alone CAN controller(單機(jī)CAN控制器) |
| 中文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 28/68頁 |
| 文件大?。?/td> | 234K |
| 代理商： | SJA1000 |
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2000 Jan 04
28
Philips Semiconductors
Product specification
Stand-alone CAN controller
SJA1000
6.4.4
C
OMMAND
R
EGISTER
(CMR)
A command bit initiates an action within the transfer layer of the CAN controller. This register is write only, all bits will
return a logic 0 when being read. Between two commands at least one internal clock cycle is needed in order to proceed.
The internal clock is half of the external oscillator frequency.
Table 13
Bit interpretation of the command register (CMR); CAN address 1
Notes
1.
Upon self reception request a message is transmitted and simultaneously received if the acceptance filter is set to
the corresponding identifier. A receive and a transmit interrupt will indicate correct self reception (see also self test
mode in mode register).
Setting the command bits CMR.0 and CMR.1 simultaneously results in sending the transmit message once.
No re-transmission will be performed in the event of an error or arbitration lost (single-shot transmission).
Setting the command bits CMR.4 and CMR.1 simultaneously results in sending the transmit message once using the
self reception feature. No re-transmission will be performed in the event of an error or arbitration lost.
Setting the command bits CMR.0, CMR.1 and CMR.4 simultaneously results in sending the transmit message once
as described for CMR.0 and CMR.1.
The moment the transmit status bit is set within the status register, the internal transmission request bit is cleared
automatically.
Setting CMR.0 and CMR.4 simultaneously will ignore the set CMR.4 bit.
This command bit is used to clear the data overrun condition indicated by the data overrun status bit. As long as the
data overrun status bit is set no further data overrun interrupt is generated.
After reading the contents of the receive buffer, the CPU can release this memory space in the RXFIFO by setting
the release receive buffer bit to logic 1. This may result in another message becoming immediately available within
the receive buffer. If there is no other message available, the receive interrupt bit is reset.
2.
3.
4.
BIT
SYMBOL
SRR
NAME
VALUE
1
FUNCTION
CMR.7
CMR.6
CMR.5
CMR.4
reserved
reserved
reserved
Self Reception Request;
notes 1 and 2
present; a message shall be transmitted and
received simultaneously
(absent)
clear; the data overrun status bit is cleared
(no action)
released; the receive buffer, representing the
message memory space in the RXFIFO is
released
(no action)
present; if not already in progress, a pending
transmission request is cancelled
(absent)
present; a message shall be transmitted
(absent)
0
1
0
1
CMR.3
CDO
Clear Data Overrun;
note 3
CMR.2
RRB
Release Receive Buffer;
note 4
0
1
CMR.1
AT
Abort Transmission;
notes 5 and 2
0
1
0
CMR.0
TR
Transmission Request;
notes 6 and 2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SJA1000/N1,112 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC STAND-ALONE CAN CONTROLLER RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| SJA1000/N1112 | 制造商:NXP Semiconductors 功能描述:IC CAN CONTROLLER 1000 DIP28 |
| SJA1000N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Stand-alone CAN controller |
| SJA1000T | 制造商:NXP Semiconductors 功能描述: |
| SJA1000T/N,112 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC STAND ALONE CAN CONTROLLER RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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