參數(shù)資料
型號(hào): SJA1000
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Stand-alone CAN controller(單機(jī)CAN控制器)
中文描述: 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁(yè)數(shù): 55/68頁(yè)
文件大?。?/td> 234K
代理商: SJA1000
2000 Jan 04
55
Philips Semiconductors
Product specification
Stand-alone CAN controller
SJA1000
Table 48
Output pin configuration; note 1
Notes
1.
2.
3.
4.
X = don’t care.
TPX is the on-chip output transistor X, connected to V
DD
.
TNX is the on-chip output transistor X, connected to V
SS
.
TXX is the serial output level on pin TX0 or TX1. It is required that the output level on the CAN-bus line is dominant
when TXD = 0 and recessive when TXD = 1.
DRIVE
TXD
OCTPX
OCTNX
OCPOLX
TPX
(2)
TNX
(3)
TXX
(4)
Float
Pull-down
X
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
off
off
off
off
off
off
on
on
off
off
on
on
off
off
on
off
off
on
off
off
off
off
on
off
off
on
float
LOW
float
float
LOW
float
HIGH
HIGH
float
LOW
HIGH
HIGH
LOW
Pull-up
Push-pull
The bit sequence (TXD) is sent via TX0 and TX1.
The voltage levels on the output driver pins depends on
both the driver characteristics programmed by OCTP,
OCTN (float, pull-up, pull-down, push-pull) and the output
polarity programmed by OCPOL.
6.5.4
C
LOCK
D
IVIDER
R
EGISTER
(CDR)
The clock divider register controls the CLKOUT frequency
for the microcontroller and allows to deactivate the
CLKOUT pin. Additionally a dedicated receive interrupt
pulse on TX1, a receive comparator bypass and the
selection between BasicCAN mode and PeliCAN mode is
made here. The default state of the register after hardware
reset is divide-by-12 for Motorola mode (00000101) and
divide-by-2 for Intel mode (00000000).
On software reset (reset request/reset mode) this register
is not influenced.
The reserved bit (CDR.4) will always reflect a logic 0.
The application software should always write a logic 0 to
this bit in order to be compatible with future features, which
may be 1-active using this bit.
Table 49
Bit interpretation of the clock divider register (CDR); CAN address 31
Note
1.
This bit cannot be written. During read-out of this register always a zero is given.
BIT 7
BIT 6
CBP
BIT 5
RXINTEN
BIT 4
(0)
(1)
BIT 3
clock off
BIT 2
CD.2
BIT 1
CD.1
BIT 0
CD.0
CAN mode
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