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參數(shù)資料
| 型號： | SLWS132 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUAD RECEIVER CHIP |
| 中文描述： | 四接收器芯片 |
| 文件頁數(shù)： | 14/46頁 |
| 文件大?。?/td> | 413K |
| 代理商： | SLWS132 |
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GRAYCHIP, INC.
- 9 -
APRIL 27, 1999
GC4014 QUAD RECEIVER CHIP
DATA SHEET REV 0.6
This document contains information which may be changed at any time without notice
3.3.6
Real Mode
The PFIR will output either complex or real data. Complex data is output at a rate equal to F
CK
/(4N) or
F
CK
/(8N) in the decimate by 4 mode. If the output samples are real, then the filter translates the output spectrum up
by multiplying the filtered data by the complex sequence +1, -j, -1, +j,
…
, and then outputting the real part at a rate
equal to F
CK
/2N. The real output mode can be used to create double sided signals out of single sideband data. The
real outputs are packed into complex words for output. The first sample of a real pair is put into the I-half and the
second is put into the Q-half. Note that the decimate by 4 mode is invalid in the real mode.
3.4
FINAL GAIN ADJUSTMENT
The final gain of each channel is adjusted by multiplying each output sample by G/32, where G is a 10bit
2’s complement gain word. Since G can range between -512 and +511, the gain adjustment will range from -16.0
to +15.98. Setting G to zero clears the channel. This provides a final gain adjustment range from -
∞
to +24 dB in
approximately 0.28 dB steps. A different gain can be specified for each channel. Note that the overall gain of the
chip is also a function of the amount of decimation programmed into the chip (N), the scale circuit setting in the CIC
filter, the coarse gain setting, the narrow mode in the CFIR, and the sum of the PFIR coefficients. The overall gain
is shown below where the first term in braces is fixed for all four channels and must be less than or equal to unity.
The terms in square brackets can be different for each channel. NARROW is “1” in the narrow CFIR mode, “0”
otherwise. See Section 7.9 for a discussion on properly setting the chip’s gain.
3.5
SUMMATION MODES
The chip can be programmed to output the four individual channels, the sum of pairs of channels, or the
sum of all four channels.These modes are used to process four real input signals, two complex input signals, or one
beamformed signal. When processing two complex input signals, the I inputs are put in channels A and C, and the
Q inputs are put in channels B and D. The summation mode then adds channels A and B together and channels C
and D together.
Summation is disabled in Sum Mode 0. In Sum Mode 1 the channel A output is replaced by the sum of
channels A and B, the channel B output is replaced by the sum of channels C and D, and the channel C and D
outputs are left alone. In Sum Mode 2 the channel A output becomes the sum of all four channels and channels B,
C and D are left alone. These modes are summarized in the following table:
Table 1: Output Summation Modes
SUM MODE
CHANNEL OUTPUT
OUT
A
OUT
B
OUT
C
OUT
D
0
CH
A
CH
B
CH
C
CH
D
1
CH
A
+ CH
B
CH
C
+ CH
D
CH
C
CH
D
2
CH
A
+ CH
B
+ CH
C
+ CH
D
CH
B
CH
C
CH
D
GAIN
N
4
2
SCALE
6
BIG_SCALE
×
56
–
+
(
)
{
}
2
COARSE
[
]
1.0
{
NARROW
0.97
×
+
}
------------------
{
}
-----
[ ]
=
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