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參數(shù)資料
| 型號： | SLWS132 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUAD RECEIVER CHIP |
| 中文描述： | 四接收器芯片 |
| 文件頁數(shù)： | 7/46頁 |
| 文件大小： | 413K |
| 代理商： | SLWS132 |
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GRAYCHIP, INC.
- 2 -
APRIL 27, 1999
GC4014 QUAD RECEIVER CHIP
DATA SHEET REV 0.6
This document contains information which may be changed at any time without notice
3.0
FUNCTIONAL DESCRIPTION
The GC4014 quad receive chip contains four identical down-conversion circuits. Each down-convert circuit
accepts a real sample rate up to 62.5 MHz, down converts a selected carrier frequency to zero, decimates the signal
rate by a programmable factor ranging from 16 to 32768 (32 to 65,536 for complex outputs), and optionally sums it
with other down converted samples. The chip outputs the four down-converted signals, or their sum. The chip
contains a user programmable output filter which can be used to arbitrarily shape the received data’s spectrum. This
filter can be used as a Nyquist receive filter for digital data transmission.
Two down-converter paths can be merged to be used as a single complex input down-conversion circuit.
The down-converters are designed to maintain over 95 dB of spur free dynamic range and over 100 dB of
out of band rejection. Each down-convert circuit accepts 16 bit inputs and produces 16 bit outputs (bit serial). The
frequencies and phase offsets of the four sine/cosine sequence generators can be independently specified, as can
the gain of each circuit. The down converters share the same bandwidth, filter coefficients and input formats. A
special mode allows the downconverters to support GSM and DAMPS blocker requirements (see Sections 7.5 and
7.6).
On chip diagnostic circuits are provided to simplify system debug and maintenance.
The chip receives configuration and control information over a microprocessor compatible bus consisting of
an 8 bit data I/O port, a 5 bit address port, a chip enable strobe, a read strobe and a write strobe. The chip’s control
registers (8 bits each) are memory mapped into the 5 bit address space of the control port.
Section 7.5 Describes a typical application, including control register values and the proper sequence of
operations required to use the chip.
3.1
CONTROL INTERFACE
The chip is configured by writing control information into sixty four control registers within the chip. The
contents of these control registers and how to use them are described in Section 5. The registers are written to or
read from using the
C[0:7]
,
A[0:4]
,
CE
,
RD
and
WR
pins. Each control register has been assigned a unique address
within the chip. This interface is designed to allow the GC4014 to appear to an external processor as a memory
mapped peripheral (the pin
RD
is equivalent to a memory chip’s
OE
pin).
An external processor (a microprocessor, computer, or DSP chip) can write into a register by setting
A[0:4]
to the desired register address, selecting the chip using the
CE
pin, setting
C[0:7]
to the desired value and then
pulsing
WR
low. The data will be written into the selected register when both
WR
and
CE
are low and will be held
when either signal goes high.
To read from a control register the processor must set
A[0:4]
to the desired address, select the chip with
the
CE
pin, and then set
RD
low. The chip will then drive
C[0:7]
with the contents of the selected register. After the
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