參數(shù)資料
型號(hào): SLWS132
廠商: Texas Instruments, Inc.
英文描述: QUAD RECEIVER CHIP
中文描述: 四接收器芯片
文件頁數(shù): 8/46頁
文件大?。?/td> 413K
代理商: SLWS132
GRAYCHIP, INC.
- 3 -
APRIL 27, 1999
GC4014 QUAD RECEIVER CHIP
DATA SHEET REV 0.6
This document contains information which may be changed at any time without notice
processor has read the value from
C[0:7]
it should set
RD
and
CE
high. The
C[0:7]
pins are turned off (high
impedance) whenever
CE
or
RD
are high or when
WR
is low. The chip will only drive these pins when both
CE
and
RD
are low and
WR
is high.
One can also ground the
RD
pin and use the
WR
pin as a read/write direction control and use the
CE
pin
as a control I/O strobe. Figure 2 shows timing diagrams illustrating both I/O modes.
Figure 2. Control I/O Timing
The setup, hold and pulse width requirements for control read or write operations are given in
Section 6.0.
The
C
,
A
,
WR
,
RD
and
CE
pins will accept either 5 volt or 3.3 volt input levels. A separate power supply
voltage pin (
V
UP
) is provided on the chip to enable this feature.
3.2
INPUT FORMAT
Both 14 bit and 16 bit input formats are accepted. In the 14 bit mode the inputs are 14 bit samples from four
different sources. In the 16 bit mode, the inputs are 16 bit samples from three different sources. In either case, a
crossbar switch allows the user to route any input to any down-converter channel. The input samples are normally
clocked into the chip at the clock rate, i.e., the input sample rate is equal to the clock rate. Input rates lower than the
clock rate can be accepted by using the zero pad mode. The zero pad mode will insert up to 15 zeroes between
CE
WR
RD
C[0-7]
A[0-5]
t
CSU
t
CDLY
t
CSU
t
CZ
READ CYCLE- NORMAL MODE
CE
WR
RD
C[0-7]
A[0-5]
t
CSU
t
CSPW
t
CSU
t
CHD
WRITE CYCLE- NORMAL MODE
WR
CE
C[0-7]
A[0-5]
t
CDLY
t
CSU
t
CZ
t
CHD
t
CHD
CE
WR
C[0-7]
A[0-5]
t
CSPW
t
CSU
t
CHD
READ CYCLE-
RD
HELD LOW
WRITE CYCLE-
RD
HELD LOW
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