參數(shù)資料
型號： SM3E-19.44M
廠商： Connor-Winfield
文件頁數(shù)： 3/36頁
文件大?。?/td> 0K
描述： IC MOD TIMING 19.440MHZ STRAT 3E
標(biāo)準(zhǔn)包裝： 1
系列： SM3
類型： 定時模塊，系統(tǒng)時鐘
PLL： 是
主要目的： 以太網(wǎng)，ADM，DSLAM，SONET/SDH，Stratum，TDM
輸入： LVCMOS
輸出： LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:3
差分 - 輸入:輸出： 無/無
頻率 - 最大： 19.44MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： 通孔
封裝/外殼： 32-DIP 模塊
包裝： 管件
其它名稱： CW643
SM3E 19.44M
SM3E19.44M
SM3E Data Sheet #:
TM054
Page 11 of 36 Rev: 04 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Detailed Description continued
Output Signals and Frequency
Output 1istheprimarychipoutput,andinlockedmodeissynchronizedtotheselectedreference.Output 1maybeanyofthe
followingfrequencies:12.96MHz,19.44MHz,25.92MHz,38.88MHz,51.84MHzor77.76MHz.
M/S_Out isan8kHzoutputavailableasaframereferenceorsynchronizationsignalforcross-coupledpairsofSM3Edevices
operatedinmaster/slavemode.Inmastermode,M/S_Outissynchronizedtotheselectedreference.Inslavemode,M/S_Outisin
phasewiththe
M/S REF offsetbythevaluewrittentothePhase_offset register(+31.75to-32nS,with.25nSresolution).M/S_Out
maybea50%dutycyclesignal,orvariablehigh-goingpulsewidth,asdeterminedbythe
Ctl_ModeandFr_Pulse_Widthregisters.
Invariablepulsewidthmode,thewidthmaybefrom1to15multiplesofthe
Output 1cycletime.SeeRegisterDescriptionsand
Operationsection.
BITS_ClkistheBITSclockoutputateither1.544MHzor2.048MHz.ItisselectedbytheT1/E1inputanditsstatemaybereadinbit
3oftheCtl_Moderegister.WhenT1/E1=1,theBITSfrequencyis1.544MHz,andwhenT1/E1=0,theBITSfrequencyis2.048MHz.
Interrupts
TheSM3Emodulesupportseightdifferentinterruptsandappearsin
INTR_EVENT (0x12)register.Eachinterruptcanbe
individuallyenabledordisabledviathe
INTR_ENABLE (0x13)register.Eachbitenablesordisablesthecorrespondinginterruptfrom
assertingthe
SPI_INTpin.InterrupteventsstillappearintheINTR_EVENT (0x12)registerindependentoftheirenablestate.All
interruptsareclearedonce
INTR_EVENT (0x12)registerisread.Theinterruptsare:
Anyreferencechangingfromavailabletonotavailable
Anyreferencechangingfromnotavailabletoavailable
M/S REFchangingfromactivitytonoactivity
M/S REFchangingfromnoactivitytoactivity
DPLLModestatuschange
Referenceswitchinautomaticreferenceselectionmode
LossofSignal
LossofLock
Interrupts and Reference Change in Autonomous Mode
Interruptscanbeusedtodeterminethecauseofareferencechangeinautonomousmode.Letusassumethatthemoduleis
currentlylockedto
REF1.ThemoduleswitchestoREF2andSPI_INTpinisasserted.TheuserreadstheINTR_EVENT (0x12)
register.
Ifthemoduleisoperatinginautonomousnon-revertivemode,thecausecanbedeterminedfrombits4,5,6and7.Bit5issetto
indicateActivereferencechange.IfBit6issetthenthecauseofthereferencechangeisLossofActiveReference.IfBit7issetthen
thecauseofthereferencechangeisaLossofLockalarmontheactivereference.
Ifthemoduleisoperatinginautonomousrevertivemode,thecausecanbedeterminedfrombits1,4,5,6and7.Bit5issetto
indicateActivereferencechange.IfBit6issetthenthecauseofthereferencechangeisLossofActiveReference.IfBit7isset
thenthecauseofthereferencechangeisaLossofLockalarmontheactivereference.IfBit1issetthenthecauseofthereference
changeistheavailabilityofahigherpriorityreference.
Note:TheDPLLModeStatusChangebit(Bit4)isalsosettoindicateachangeinDPLL_STATUS (0x11)register,duringan
interruptcausedbyareferencechange.Thedatain
DPLL_STATUS (0x11)registerhoweverisnotusefulindeterminingthecauseof
areferencechange.Thisisbecausebits0-2ofthisregisteralwaysreflectsthestatusofthecurrentactivereferenceandhencecannot
beusedtodeterminethestatusofthelastactivereference.
Interrupts in Manual Mode
Inmanualoperatingmode,whentheactivereferencefailsduetoaLossofSignalorLossofLockalarm,aninterruptisgenerated.
Forexample,incaseofaLossofSignal,bits4and6of
INTR_EVENT (0x12) registerwouldbesettoindicateLossofSignaland
DPLLModeStatusChange.Theusermaychoosetoreadthe
DPLL_STATUS (0x11)register,thoughinmanualmodebit6ofINTR_
EVENT (0x12)registerisamirrorofbit0ofDPLL_STATUS (0x11)register.ThisholdstrueforaLossofLockalarm,wherebit7of
INTR_EVENT (0x12) registerisamirrorofbit1ofDPLL_STATUS (0x11)register.
Internal Clock Calibration
Theinternalclockmaybecalibratedbywritingafrequencyoffsetv.s.nominalfrequencyintotheCalibrationregister.This
calibrationisusedbythesynchronizationsoftwaretocreateafrequencycorrectedfromtheactualinternalclockoutputbythevalue
writtentotheCalibrationregister.Seeregisterdescriptions.
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