參數(shù)資料
型號(hào)： SM3E-19.44M
廠商： Connor-Winfield
文件頁(yè)數(shù)： 36/36頁(yè)
文件大?。?/td> 0K
描述： IC MOD TIMING 19.440MHZ STRAT 3E
標(biāo)準(zhǔn)包裝： 1
系列： SM3
類(lèi)型： 定時(shí)模塊，系統(tǒng)時(shí)鐘
PLL： 是
主要目的： 以太網(wǎng)，ADM，DSLAM，SONET/SDH，Stratum，TDM
輸入： LVCMOS
輸出： LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:3
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 19.44MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 通孔
封裝/外殼： 32-DIP 模塊
包裝： 管件
其它名稱(chēng)： CW643
SM3E 19.44M
SM3E19.44M
SM3E Data Sheet #:
TM054
Page 9 of 36 Rev: 04 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Reference Input Quality Monitoring
Eachreferenceinputismonitoredforsignalpresenceandfrequencyoffset.Signalpresenceforthe
Ref1-8inputsisindicatedin
the
Ref_ActivityregisterandsignalpresencefortheM/S REFisindicatedinbit0oftheM/S REF_Activityregister.Thefrequency
offsetbetweenthe
Ref1-8inputsandthecalibratedlocaloscillatorisavailableintheRef_Frq_Offsetregisters(8).RegisterRef_
Pullin_Stsindicates,foreachoftheRef1-8inputs,ifthereferenceiswithinthemaximumpull-inrange.Themaximumpull-inrange
isindicatedinregister
Max_Pullin_Range,andmaybesetin0.1ppmincrements.Typically,itwouldbesetaccordingtothevalues
specifiedbythestandards(GR-1244)appropriatefortheparticularstratumofoperation.
The
Ref_Qualifiedregistercontainsthe“anded”conditionoftheRef_ActivityandRef_Pullin_StsregistersforeachoftheRef1-8
inputs,qualifiedfor10seconds.Whenareferencesignalhasbeenpresentfor>10secondsandiswithinthepull-inrange,it’sbitisset.
The
Ref_Availableregistercontainsthe“anded”conditionoftheRef_QualifiedregisterandtheRef_Maskregister,andtherefore
representstheavailabilityofareferenceforselectionwhenautomaticreferenceandoperationalmodeselectionisenabled.
Reference Input Selection, Frequencies, and Mode Selection
Oneofeightreferenceinputsignals(
Ref 1-8)areselectedforsynchronizationinMastermode(asbelowintheOp_Moderegister
description.0x05).
Ref 1-8mayeachbe8kHz,1.544MHz,2.048MHz,12.96MHz,19.44MHz,25.92MHz,38.88MHz,51.84MHz
or77.76MHz.
Referencefrequenciesareauto-detectedandthedetectedfrequencycanbereadfromthe
Ref_Frq_Priority registers(See
Register Descriptions and Operationsection).
Activereferenceandoperationalmodeselectionmaybemanualorautomatic,asdeterminedbybit1inthe
Ctl_Moderegister.In
manualmode,registerwritesto
Op_Modeselectthereferenceandmode.Theresetdefaultismanualmode.
TheM/SREFinputforslaveoperationisfrequencyauto-detectedandmaybe8kHz,1.544MHz,2.048MHz,12.96MHz,19.44MHz,
25.92MHz,38.88MHz,51.84MHzor77.76MHz.SignalpresenceandfrequencyfortheM/SREFinputisindicatedinbits0-3ofthe
M/S REF_Activityregister.
Inautomaticmode,thereferenceisselectedaccordingtotheprioritieswrittentotheeight
Ref_Frq_Priorityregisters.Individual
referencesmaybemaskedforuse/non-useaccordingtothe
Ref_Maskregister.Areferencemayonlybeselectedifitis“available”
-thatis,itisqualified,asindicatedinthe
Ref_Qualified register,andisnotmasked(SeeReference Input Quality Monitoring and
Register Descriptions and Operation sections).
Furthermore,Bit3ofeach
Ref_Frq_Priority registerwilldetermineifthatreferenceisrevertiveornon-revertive.Whenareference
fails,thenexthighestpriority“available”(signalpresent,non-masked,andacceptablefrequencyoffset)referencewillbeselected.
Whenareferencereturns,itwillbeswitchedtoonlyifitisofhigherpriorityandthecurrentactivereferenceismarked“Revertive”.
Additionally,thereversionisdelayedaccordingtothevaluewrittentothe
Ref_Rev_Delayregister(From0to255minutes).
Detailed Description continued
Serial Interface Timing
Table 4
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
t
CS
SPI_EnablelowtoSPI_CLKlow
15
-
ns
t
CH
SPI_CLKhightime
25
-
ns
t
CL
SPI_CLKlowtime
25
-
ns
t
RWs
Read/Writesetuptime
15
-
ns
t
RWh
Read/Writeholdtime
15
-
ns
t
DRDY
Dataready
-
25
ns
t
HLD
DataHold
15
-
ns
t
CSTRI
ChipSelecttodatatri-state
5
-
ns
t
CSMIN
Minimumdelaybetweensuccessiveaccesses 300
-
ns
Note:TheSPIportshouldnotbeaccesseduntil1200msafterresethastransitionedfromlowtoahighstate.
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