參數(shù)資料
型號(hào)： SM5964Ihhk
廠商： Electronic Theatre Controls, Inc.
英文描述： 8 - bit single chip microcontroller with 64KB flash & 1K byte RAM embedded
中文描述： 8 -位單片機(jī)具有64KB閃存
文件頁數(shù)： 13/28頁
文件大?。?/td> 539K
代理商： SM5964IHHK
July 2002
Specifications subject to change without notice,contact your sales representatives for the most recent information.
13/28
PID 5964 07/02
SyncMOS Technologies Inc. SM5964
One page of flash memory is 512 byte.
To perform byte program/page erase ISP function, user need to specify flash address at first. When performing page erase
function, SM5964 will erase entire page which flash address indicated by ISPFAH & ISPFAL registers located within the page.
e.g. flash address: $XYMN
page erase function will erase from $XY00 to $X(Y+1)FF (Y:even number), or
page erase function will erase from $X(Y-1) 00 to $XYFF (Y:odd number)
To perform the chip erase ISP function, SM5964 will erase all the flash program memory except the ISP service program
space, also, SM5964 will un-protect the flash memory automatically. To perform chip protect ISP function, the SM5964 flash
memory content will be read #00H.
e.g. ISP service program to do the byte program - to program #22H to the address $1005H
MOV SCONF,#04H ; enable SM5964 ISP function
MOV ISPFAH,#10H ; set flash address-high, 10H
MOV ISPFAL,#05H ; set flash address-low, 05H
MOV ISPFD,#22H ; set flash data to be programmed, data = 22H
MOV ISPC,#80H ; start to program #22H to the flash address $1005H
; after byte program finished, START bit of ISPC will be reset to 0 automatically
; program counter then point to the next instruction
ISP Registers - System Control Register (SCONF,$BF)
The bit 2 (ISPE) of SCONF is ISP enable bit. User can enable overall SM5964 ISP function by setting ISPE bit to 1, to disable
overall ISP function by set ISPE to 0.
The function of ISPE behaves like a security key. User can disable overall ISP function to prevent software program be erased
accidentally.
4. Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is
useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop
or runaway. The WDT function can help user software recover form abnormal software condition. The WDT is different from
Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT
counter. User should check WDR bit of SCONF register whenever unpredicted reset happened
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit2~bit0
(PS2~PS0) of Watch Dog Timer Control Register (WDTC) should be set accordingly.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count
with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when overflows. The WDTE bit
will be cleared to 0 automatically when SM5964 been reset, either hardware reset or WDT reset.
bit-7
bit-0
Read:
Write:
Reset value:
WDR
Unused
Unused
Unused
Unused
ISPE
OME
ALEI
0
*
*
*
*
0
1
0
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