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參數(shù)資料
| 型號： | SM5964Ihhk |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8 - bit single chip microcontroller with 64KB flash & 1K byte RAM embedded |
| 中文描述： | 8 -位單片機具有64KB閃存 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 539K |
| 代理商： | SM5964IHHK |
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July 2002
Specifications subject to change without notice,contact your sales representatives for the most recent information.
15/28
PID 5964 07/02
SyncMOS Technologies Inc. SM5964
the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle frame. The
number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the BRM is to
generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit SPWM clock
speed. The PDIV[1:0] settings of SPWMC ($A3) register are divident of Fosc to be SPWM clock, Fosc/2^(PDIV[1:0]+1).
The SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is [Fosc/2^(PDIV[1:0]+1)]/32.
5. Reduce EMI Function
The SM5964 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will
inhibit the clock signal in Fosc/6Hz output to the ALE pin.
6. Specific Pulse Width Modulation (SPWM)
The Specific Pulse Width Modulation (SPWM) module has five 8-bit channels, each channel contains a 8-bit wide SPWM
data register (SPWMD) to decide number of continuous pulses within a SPWM frame cycle.
6.1 SPWM Function Description:
Each 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit binary
rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse length of
6.2 SPWM Registers - P1CON, SPWMC, SPWMR[4:0]
SPWM Registers - Port1 Configuration Register (P1CON, $9B)
SPWM[4:0]E : When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit
reset to zero, the corresponding SPWM pin is active as I/O pin. Five bits are cleared upon reset.
SPWM Registers - SPWM Control Register (SPWMC, $A3)
PDIV[1:0] : These two bits is 2’s power parameter to form a frequency divider for input clock.
bit-7
bit-0
Read:
Write:
Reset value:
SPWM4E
SPWM3E
SPWM2E
SPWM1E
SPWM0E
Unused
Unused
Unused
0
0
0
0
0
*
*
*
bit-7
bit-0
Read:
Write:
Reset value:
Unused
Unused
Unused
Unused
Unused
Unused
PDIV1
PDIV0
*
*
*
*
*
*
0
0
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