參數(shù)資料
型號(hào)： SM5964Ihhk
廠商： Electronic Theatre Controls, Inc.
英文描述： 8 - bit single chip microcontroller with 64KB flash & 1K byte RAM embedded
中文描述： 8 -位單片機(jī)具有64KB閃存
文件頁(yè)數(shù)： 16/28頁(yè)
文件大小： 539K
代理商： SM5964IHHK
July 2002
Specifications subject to change without notice,contact your sales representatives for the most recent information.
16/28
PID 5964 07/02
SyncMOS Technologies Inc. SM5964
Ver 1.0
SPWM Data Register (SPWMD[4:0], $AC, $A4 ~$A7)
SPWMD[4:0][4:0] : content of SPWM Data Register. It determines duty cycle of SPWM output waveform.
BRM[4:0][2:0] : will insert certain narrow pulses among an 8-SPWM-cycle frame
Example of SPWM timing diagram :
MOV SPWMD0 , #83H ; SPWMD0[4:0]=10h (=16T high, 16T low), BRM0[2:0] = 3
MOV P1CON , #08H ; Enable P1.3 as PWM output pin
PDIV1
0
0
1
1
PDIV0
0
1
0
1
Divider
2
4
8
16
SPWM clock, Fosc=20MHz
10MHz
5MHz
2.5MHz
1.25MHz
SPWM clock, Fosc=24MHz
12MHz
6MHz
3MHz
1.5MHz
bit-7
bit-0
Read:
Write:
Reset value:
SPWMD
[4:0]4
SPWMD
[4:0]3
SPWMD
[4:0]2
SPWMD
[4:0]1
SPWMD
[4:0]0
BRM
[4:0]2
BRM
[4:0]1
BRM
[4:0]0
0
0
0
0
0
0
0
0
N = BRM[4:0][2:0]
XX1
X1X
1XX
Number of SPWM cycles inserted in an 8-cycle frame
1
2
4
16T
16T
16T
16T
16T
16T
16T
16T
32T
32T
32T
32T
32T
32T
32T
32T
1st cycle frame 2nd cycle frame 3rd cycle frame
4th cycle frame 5th cycle frame
6th cycle frame
7th cycle frame
8th cycle frame
1T
(narrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3)
1T
1T
SPWM clock = 1 / T = Fosc / 2^(PDIV+1)
The SPWM output cycle frame frequency = SPWM clock / 32 = [Fosc/2^(PDIV+1)]/32
If user use Fosc=20MHz, PDIV[1:0] of SPWMC=#03H, then
SPWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz
SPWM output cycle frame frequency = (20MHz/2^4)/32=39.1KHz
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