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參數(shù)資料
| 型號： | SN54ABTH18652A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Scan Test Devices With 18 Bit Universal Bus Transceivers and Registers( 掃描檢測裝置，帶18位總線收發(fā)器和寄存器) |
| 中文描述： | 掃描測試設(shè)備與18位通用總線收發(fā)器和寄存器（掃描檢測裝置，帶18位總線收發(fā)器和寄存器） |
| 文件頁數(shù)： | 17/36頁 |
| 文件大?。?/td> | 848K |
| 代理商： | SN54ABTH18652A |
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SN54ABTH18652A, SN54ABTH182652A, SN74ABTH18652A, SN74ABTH182652A
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS167D – AUGUST 1993 – REVISED JULY 1996
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each
falling edge of TCK. Figures 6 and 7 illustrate the 36-bit linear-feedback shift-register algorithms through which
the patterns are generated. An initial seed value should be scanned into the BSR before performing this
operation. A seed value of all zeroes does not produce additional patterns.
=
1B8-I/O
1B7-I/O
1B6-I/O
1B5-I/O
1B4-I/O
1B3-I/O
1B2-I/O
1B1-I/O
1B9-I/O
1A7-I/O
1A6-I/O
1A5-I/O
1A4-I/O
1A3-I/O
1A2-I/O
1A1-I/O
1A8-I/O
1A9-I/O
2A7-I/O
2A6-I/O
2A5-I/O
2A4-I/O
2A3-I/O
2A2-I/O
2A1-I/O
2A8-I/O
2A9-I/O
2B8-I/O
2B7-I/O
2B6-I/O
2B5-I/O
2B4-I/O
2B3-I/O
2B2-I/O
2B1-I/O
2B9-I/O
Figure 6. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 1)
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| SN54ABTH18652AHV | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS |
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