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參數(shù)資料
| 型號： | SP791EP |
| 英文描述： | Low Power Microprocessor Supervisory with Battery Switch-Over |
| 中文描述： | 低功耗微處理器監(jiān)控與電池開關過 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大小： | 202K |
| 代理商： | SP791EP |
15
SP791DS/08 SP791 Low Power Microprocessor Supervisory with Battery Switch-Over
Copyright 2000 Sipex Corporation
Leakage current through the capacitor charging
diode and the
SP791
internal power diode even-
tually discharges the capacitor to V
CC
. Also, if
V
CC
and V
BATT
start from 0.5V above the reset
threshold and power is lost at V
CC
, the capacitor
on V
BATT
discharges through V
CC
until V
BATT
reaches the reset threshold; the
SP791
then
switches to battery-backup mode.
USING SEPARATE POWER SUPPLIES
FOR V
BATT
AND V
CC
If using separate power supplies for V
CC
and
V
BATT
, V
BATT
must be less than 0.3V above V
CC
when V
CC
is above the reset threshold. As
described in the previous section, if V
BATT
ex-
ceeds this limit and power is lost at V
CC
, current
flows continuously from V
BATT
to V
CC
via the
V
BATT
-to-V
OUT
diode and the V
OUT
-to-V
CC
switch until the circuit is broken.
ALTERNATIVE CHIP-ENABLE GATING
Using memory devices with CE and CE inputs
allows the
SP791
CE loop to be bypassed. To do
this, connect CE IN to ground, pull up CE
OUT
to V
OUT
, and connect CE OUT to the CE input
of each memory device as shown in
Figure 13
.
The CE input of each part then connects directly
to the chip-select logic, which does not have to
be gated by the
SP791
.
ADDING HYSTERESIS TO THE
POWER-FAIL COMPARATOR
Hysteresis adds a noise margin to the power-fail
comparator and prevents repeated triggering of
PFO when VIN is near the trip point.
Figure 14
shows how to add hysteresis to the power-fail
comparator. Select the ratio of R1 to R2 such
that PFI sees 1.25V when VIN falls to the de-
sired trip point (VTRIP). Resistor R3 adds hys-
teresis. It will typically be an order of magni-
tude greater than R1 or R2. The current through
R1 and R2 should be at least 1
μ
A to ensure that
the 25nA (max) PFI input current does not shift
the trip point. R3 should be larger than 10k
to
prevent it from loading down the PFO pin. Ca-
pacitor C1 adds additional noise rejection.
MONITORING A NEGATIVE VOLTAGE
The power-fail comparator can be used to moni-
tor a negative supply voltage using the circuit
shown in
Figure 15
. When the negative supply
is valid, PFO is low. When the negative supply
voltage drops, PFO goes high. This circuit's ac-
curacy is affected by the PFI threshold tolerance,
the V
CC
voltage, and resistors R1 and R2.
BACKUP-BATTERY REPLACEMENT
The backup battery may be disconnected while
V
CC
is above the reset threshold. No precautions
are necessary to avoid spurious reset pulses.
Figure 14. Adding Hysteresis to the Power-Fail Comparator
Figure 13. Alternate CE Gating
Corporation
CE
IN
CE
OUT
V
OUT
GND
CE
CE
CE
CE
CE
CE
CE
CE
Rp
*
MAXIMUM Rp VALUE DEPENDS ON
ACTIVE-HIGH CE
LINES FROM LOGIC
RAM 1
RAM 2
RAM 3
RAM 4
VIN
R1
R2
R3
C1*
+5V
PFI
PFO
GND
TO
μ
P
+5V
PFO
OV
OV
* NOISE REJECTION
V
L
V
TRIP
V
H
R1 + R2
(
)
R2 II R3
R1 + R2 II R3
)
L
- 1.25 +
V
C orporation
Vcc
V
H
= 1.25
V
TRIP
= 1.25 *
V
IN
=
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