參數(shù)資料
型號: SP791EP
英文描述: Low Power Microprocessor Supervisory with Battery Switch-Over
中文描述: 低功耗微處理器監(jiān)控與電池開關(guān)過
文件頁數(shù): 8/19頁
文件大?。?/td> 202K
代理商: SP791EP
SP791DS/08 SP791 Low Power Microprocessor Supervisory with Battery Switch-Over
Copyright 2000 Sipex Corporation
8
2) Manual-Reset input
Manually resets
RESET output
3) Power Fail Comparator
Provides for power-
fail warning and low-battery detection, or
monitors another power supply.
4) Watchdog function
Monitors
μ
P activity
where the watchdog output goes to a logic
LOW state if the watchdog input is not toggled
for a period greater than the timeout period.
5) Internal switch
Switches over from V
to
V
if the V
falls below the reset thresh-
old and below V
BATT
.
MANUAL RESET INPUT
Many microprocessor or microcontroller prod-
ucts include manual-reset capability, allowing
the operator or test technician to initiate a reset.
The Manual Reset Input (MR) can be connected
directly to a switch, without an external pull-up
resistor. It connects to a 1.25V comparator, and
has an internal pull-up to V
OUT
as shown in
Fig-
ure 1
. The propagation delay from asserting MR
to RESET being asserted is 7us typical. Pulsing
FEATURES
The
SP791
is a microprocessor (
μ
P) supervi-
sory circuit that monitors the power supplied to
digital circuits such as microprocessors,
microcontrollers, or memory. The
SP791
is an
ideal solution for portable, battery-powered
equipment that require power supply monitor-
ing. The
SP791
watchdog functions will con-
tinuously oversee the operational status of a sys-
tem. Implementing the
SP791
will reduce the
number of components and overall complexity
in a design that requires power supply monitor-
ing circuitry. The operational features and ben-
efits of the
SP791
are described in more detail
below.
THEORY OF OPERATION
The
SP791
is a complete
μ
P supervisor IC and
provides the following main functions:
1)
μ
P reset
RESET output is asserted during
power fluctuations such as power-up, power-
down, and brown out conditions, and is guar-
anteed to be in the correct state for V
CC
down
to 1V.
Figure 2. Manual-Reset Timing Diagram
Typical Operating Circuit
Figure 3. Diode "OR" connections allow multiple reset
sources to connect to MR.
C orporation
V
cc
V
BATT
BATT
SWT
V
OUT
CE
OUT
MR
CE
IN
PFI
PFO
GND
WDI
LOWLINE
RESET
WDO
UNREGULATED
OTHER SYSTEM
0.47F
ADDRESS
0.1
μ
F
+5V
0.1
μ
F
CMOS
AO-P
I/O
NMI
RESET
INT
UNREGULATED
MANUAL RESET
OTHER
RESET
SOURCES
*
DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS
*
*
MR
C orporation
MR
RESET
CE
IN
0V
CE
OUT
25
μ
s
MIN
7
μ
s
TYP
15
μ
s
TYP
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