參數(shù)資料
型號： SST89C58RC-40-I-TQJE
廠商： Microchip Technology
文件頁數(shù)： 2/88頁
文件大?。?/td> 0K
描述： IC MCU 8BIT FLASH 40TQFP
標(biāo)準(zhǔn)包裝： 160
系列： FlashFlex®
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： EBI/EMI，I²C，SMBus，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
2011 Silicon Storage Technology, Inc.
DS25100A
12/11
10
FlashFlex MCU
SST89C58RC
Data Sheet
A Microchip Technology Company
Data RAM Memory
The data RAM has 1KByte of internal memory. The first 256 Bytes are available by default. The second
256 Bytes are enabled by clearing the EXTRAM bit in the AUXR register. The RAM can be addressed
up to 64 KByte for external data memory.
Expanded Data RAM Addressing
The SST89C58RC has the capability of 1 KByte of RAM. See Figure 6.
The device has four sections of internal data memory:
1.
The lower 128 Bytes of RAM (00H to 7FH) are directly and indirectly addressable.
2.
The higher 128 Bytes of RAM (80H to FFH) are indirectly addressable.
3.
The special function registers (80H to FFH) are directly addressable only.
4.
The expanded RAM of 768 Bytes (00H to 2FFH) is indirectly addressable by the move
external instruction (MOVX) and clearing the EXTRAM bit. (See “Auxiliary Register
(AUXR)” in Section , “Special Function Registers”)
Since the upper 128 bytes occupy the same addresses as the SFRs, the RAM must be accessed indi-
rectly. The RAM and SFRs space are physically separate even though they have the same addresses.
When instructions access addresses in the upper 128 bytes (above 7FH), the MCU determines
whether to access the SFRs or RAM by the type of instruction given. If it is indirect, then RAM is
accessed. If it is direct, then an SFR is accessed. See the examples below.
Indirect Access:
MOV@R0, #data; R0 contains 90H
Register R0 points to 90H which is located in the upper address range. Data in “#data” is written to
RAM location 90H rather than port 1.
Direct Access:
MOV90H, #data; write data to P1
Data in “#data” is written to port 1. Instructions that write directly to the address write to the SFRs.
To access the expanded RAM, the EXTRAM bit must be cleared and MOVX instructions must be used.
The extra 768 Bytes of memory is physically located on the chip and logically occupies the first 768
bytes of external memory (addresses 000H to 2FFH).
When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX instruction in combi-
nation with any of the registers R0, R1 of the selected bank or DPTR. Accessing the expanded RAM
does not affect ports P0, P3.6 (WR#), P3.7 (RD#), or P2. With EXTRAM = 0, the expanded RAM can
be accessed as in the following example.
Expanded RAM Access (Indirect Addressing only):
MOVX@DPTR, A; DPTR contains 0A0H
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