參數(shù)資料
型號(hào)： SST89C58RC-40-I-TQJE
廠商： Microchip Technology
文件頁(yè)數(shù)： 59/88頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8BIT FLASH 40TQFP
標(biāo)準(zhǔn)包裝： 160
系列： FlashFlex®
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： EBI/EMI，I²C，SMBus，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
2011 Silicon Storage Technology, Inc.
DS25100A
12/11
62
FlashFlex MCU
SST89C58RC
Data Sheet
A Microchip Technology Company
Watchdog timer
The programmable Watchdog Timer (WDT) is for fail safe protection against software deadlock and for
automatic recovery.
The Watchdog timer is utilized as a watchdog or a timer. To use the Watchdog timer as a watchdog, set
WDRE (WDTC[3]) to ‘1’. To use the Watchdog timer as a timer only, set WDRE to ‘0’ so timer overflows
generate an interrupt. Set EWD (IEA[6]) to ‘1’ to enable the interrupt.
Watchdog Timer Mode
To protect the system against software deadlock, WDT (WDTC[1]) should be refreshed within a user-
defined time period. Without a periodic refresh, an internal hardware reset will initiate when WDRE
(WDTC[3]) = 1). Only a power-on reset clears the WDRE bit.
Any Write to WDTC must be preceded by a correct feed sequence. If WDTON (WDTC[6])=0, the start
or stop of the watchdog is controlled by SWDT (WDTC[0]). If WDTON = 1, the watchdog starts regard-
less of SWDT and cannot be stopped until overflowed.
The upper 8 bits of the time base register (WDTD) is used as the reload register of the counter. When
WDT (WDTC[1]) is set to ‘1’, the content of WDTD is loaded into the watchdog counter and the pres-
caler is cleared.
If a watchdog reset occurs, the reset pin will output at least 196 system clocks. The code execution will
begin immediately after the reset cycle.
The WDTS flag bit is set by the Watchdog timer overflow and can only be cleared by power-on reset.
Users can also clear the WDTS bit by writing ‘1’ to it following a correct feed sequence.
Pure Timer Mode
In Timer mode, the WDTC and WDTD can be written at any time without a feed sequence. Setting or
clearing the SWDT bit will start or stop the counter. A timer overflow will set the WDTS bit. Writing ‘1’ to
this bit clears it. When an overflow occurs, the content of WDTD is reloaded into the counter and the
Watchdog timer immediately begins to count again. If the interrupt is enabled, an interrupt will occur
when the timer overflows. The vector address is 053H and it has a nine-level priority by default. A feed
sequence is not required in this mode.
Clock Source
The WDT in the device uses the system clock (XTAL1) as its time base, making it a watchdog counter
rather than a Watchdog timer. The WDT register will increment every 344,064 crystal clocks. The
upper 8-bits of the time base register (WDTD) are used as the reload register of the WDT.
Figure 23 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control Watchdog
timer operation.
The time-out period of the WDT is calculated as follows:
Period = (255 - WDTD) * 344064 * 1/fCLK (XTAL1)
where WDTD is the value loaded into the WDTD register and fOSC is the oscillator frequency.
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